RE: [PATCH v3 05/10] dt-bindings: clock: Document RZ/G3L SoC

From: Biju Das

Date: Tue Feb 17 2026 - 07:06:27 EST

Hi all,

> -----Original Message-----
> From: Biju <biju.das.au@xxxxxxxxx>
> Sent: 03 February 2026 10:30
> Subject: [PATCH v3 05/10] dt-bindings: clock: Document RZ/G3L SoC
>
> From: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
>
> Document the device tree bindings for the Renesas RZ/G3L SoC Clock Pulse Generator (CPG). RZ/G3L CPG
> is similar to RZ/G2L CPG but has 5 clocks compared to 1 clock on other SoCs.
>
> Also define RZ/G3L (R9A08G046) Clock Pulse Generator Core Clock, module clock outputs, as listed in
> section 4.4.2 ("Clock List r1.00") and add Reset definitions referring to registers CPG_RST_* in
> Section 4.4.3
> ("Register") of the RZ/G3L Hardware User's Manual (Rev.1.00 Oct, 2025).
>
> Acked-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
> Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> ---
> v2->v3:
> * Added macros R9A08G046_ETH{0,1}_CLK_{TX,RX}_I_RMII.
> * Keep the tag from Conor as it is trivial change for just adding macros.
> v1->v2:
> * Documented external ethernet clocks as it is a clock source for MUX
> inside CPG
> * Updated commit description.
> * Keep the tag from Conor as it is trivial change for adding more
> clks.
> ---
> .../bindings/clock/renesas,rzg2l-cpg.yaml | 40 +-
> include/dt-bindings/clock/r9a08g046-cpg.h | 343 ++++++++++++++++++
> 2 files changed, 378 insertions(+), 5 deletions(-) create mode 100644 include/dt-
> bindings/clock/r9a08g046-cpg.h
>
> diff --git a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
> b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
> index 8c18616e5c4d..c0ce687d83ee 100644
> --- a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
> +++ b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
> @@ -28,19 +28,30 @@ properties:
> - renesas,r9a07g044-cpg # RZ/G2{L,LC}
> - renesas,r9a07g054-cpg # RZ/V2L
> - renesas,r9a08g045-cpg # RZ/G3S
> + - renesas,r9a08g046-cpg # RZ/G3L
> - renesas,r9a09g011-cpg # RZ/V2M
>
> reg:
> maxItems: 1
>
> clocks:
> - maxItems: 1
> + minItems: 1
> + items:
> + - description: Clock source to CPG can be either from external clock
> + input (EXCLK) or crystal oscillator (XIN/XOUT).
> + - description: ETH0 TXC clock input
> + - description: ETH0 RXC clock input
> + - description: ETH1 TXC clock input
> + - description: ETH1 RXC clock input
>
> clock-names:
> - description:
> - Clock source to CPG can be either from external clock input (EXCLK) or
> - crystal oscillator (XIN/XOUT).
> - const: extal
> + minItems: 1
> + items:
> + - const: extal
> + - const: eth0_txc_tx_clk
> + - const: eth0_rxc_rx_clk
> + - const: eth1_txc_tx_clk
> + - const: eth1_rxc_rx_clk
>
> '#clock-cells':
> description: |
> @@ -74,6 +85,25 @@ required:
> - '#power-domain-cells'
> - '#reset-cells'
>
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: renesas,r9a08g046-cpg
> + then:
> + properties:
> + clocks:
> + minItems: 5
> + clock-names:
> + minItems: 5
> + else:
> + properties:
> + clocks:
> + maxItems: 1
> + clock-names:
> + maxItems: 1
> +
> additionalProperties: false
>
> examples:
> diff --git a/include/dt-bindings/clock/r9a08g046-cpg.h b/include/dt-bindings/clock/r9a08g046-cpg.h
> new file mode 100644
> index 000000000000..ca484e065bbe
> --- /dev/null
> +++ b/include/dt-bindings/clock/r9a08g046-cpg.h
> @@ -0,0 +1,343 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> + *
> + * Copyright (C) 2026 Renesas Electronics Corp.
> + */
> +#ifndef __DT_BINDINGS_CLOCK_R9A08G046_CPG_H__
> +#define __DT_BINDINGS_CLOCK_R9A08G046_CPG_H__
> +
> +#include <dt-bindings/clock/renesas-cpg-mssr.h>
> +
> +/* R9A08G046 CPG Core Clocks */
> +#define R9A08G046_CLK_I 0
> +#define R9A08G046_CLK_IC0 1
> +#define R9A08G046_CLK_IC1 2
> +#define R9A08G046_CLK_IC2 3
> +#define R9A08G046_CLK_IC3 4
> +#define R9A08G046_CLK_P0 5
> +#define R9A08G046_CLK_P1 6
> +#define R9A08G046_CLK_P2 7
> +#define R9A08G046_CLK_P3 8
> +#define R9A08G046_CLK_P4 9
> +#define R9A08G046_CLK_P5 10
> +#define R9A08G046_CLK_P6 11
> +#define R9A08G046_CLK_P7 12
> +#define R9A08G046_CLK_P8 13
> +#define R9A08G046_CLK_P9 14
> +#define R9A08G046_CLK_P10 15
> +#define R9A08G046_CLK_P13 16
> +#define R9A08G046_CLK_P14 17
> +#define R9A08G046_CLK_P15 18
> +#define R9A08G046_CLK_P16 19
> +#define R9A08G046_CLK_P17 20
> +#define R9A08G046_CLK_P18 21
> +#define R9A08G046_CLK_P19 22
> +#define R9A08G046_CLK_P20 23
> +#define R9A08G046_CLK_M0 24
> +#define R9A08G046_CLK_M1 25
> +#define R9A08G046_CLK_M2 26
> +#define R9A08G046_CLK_M3 27
> +#define R9A08G046_CLK_M4 28
> +#define R9A08G046_CLK_M5 29
> +#define R9A08G046_CLK_M6 30
> +#define R9A08G046_CLK_AT 31
> +#define R9A08G046_CLK_B 32
> +#define R9A08G046_CLK_ETHTX01 33
> +#define R9A08G046_CLK_ETHTX02 34
> +#define R9A08G046_CLK_ETHRX01 35
> +#define R9A08G046_CLK_ETHRX02 36
> +#define R9A08G046_CLK_ETHRM0 37
> +#define R9A08G046_CLK_ETHTX11 38
> +#define R9A08G046_CLK_ETHTX12 39
> +#define R9A08G046_CLK_ETHRX11 40
> +#define R9A08G046_CLK_ETHRX12 41
> +#define R9A08G046_CLK_ETHRM1 42
> +#define R9A08G046_CLK_G 43
> +#define R9A08G046_CLK_HP 44
> +#define R9A08G046_CLK_SD0 45
> +#define R9A08G046_CLK_SD1 46
> +#define R9A08G046_CLK_SD2 47
> +#define R9A08G046_CLK_SPI0 48
> +#define R9A08G046_CLK_SPI1 49
> +#define R9A08G046_CLK_S0 50
> +#define R9A08G046_CLK_SWD 51
> +#define R9A08G046_OSCCLK 52
> +#define R9A08G046_OSCCLK2 53
> +#define R9A08G046_CLK_P4_DIV2 54
> +
> +/* R9A08G046 Module Clocks */
> +#define R9A08G046_CA55_SCLK 0
> +#define R9A08G046_CA55_PCLK 1
> +#define R9A08G046_CA55_ATCLK 2
> +#define R9A08G046_CA55_GICCLK 3
> +#define R9A08G046_CA55_PERICLK 4
> +#define R9A08G046_CA55_ACLK 5
> +#define R9A08G046_CA55_TSCLK 6
> +#define R9A08G046_CA55_CORECLK0 7
> +#define R9A08G046_CA55_CORECLK1 8
> +#define R9A08G046_CA55_CORECLK2 9
> +#define R9A08G046_CA55_CORECLK3 10
> +#define R9A08G046_SRAM_ACPU_ACLK0 11
> +#define R9A08G046_SRAM_ACPU_ACLK1 12
> +#define R9A08G046_SRAM_ACPU_ACLK2 13
> +#define R9A08G046_GIC600_GICCLK 14
> +#define R9A08G046_IA55_CLK 15
> +#define R9A08G046_IA55_PCLK 16
> +#define R9A08G046_MHU_PCLK 17
> +#define R9A08G046_SYC_CNT_CLK 18
> +#define R9A08G046_DMAC_ACLK 19
> +#define R9A08G046_DMAC_PCLK 20
> +#define R9A08G046_OSTM0_PCLK 21
> +#define R9A08G046_OSTM1_PCLK 22
> +#define R9A08G046_OSTM2_PCLK 23
> +#define R9A08G046_MTU_X_MCK_MTU3 24
> +#define R9A08G046_POE3_CLKM_POE 25
> +#define R9A08G046_GPT_PCLK 26
> +#define R9A08G046_POEG_A_CLKP 27
> +#define R9A08G046_POEG_B_CLKP 28
> +#define R9A08G046_POEG_C_CLKP 29
> +#define R9A08G046_POEG_D_CLKP 30
> +#define R9A08G046_WDT0_PCLK 31
> +#define R9A08G046_WDT0_CLK 32
> +#define R9A08G046_WDT1_PCLK 33
> +#define R9A08G046_WDT1_CLK 34
> +#define R9A08G046_WDT2_PCLK 35
> +#define R9A08G046_WDT2_CLK 36
> +#define R9A08G046_XSPI_HCLK 37
> +#define R9A08G046_XSPI_ACLK 38
> +#define R9A08G046_XSPI_CLK 39
> +#define R9A08G046_XSPI_CLKX2 40
> +#define R9A08G046_SDHI0_IMCLK 41
> +#define R9A08G046_SDHI0_IMCLK2 42
> +#define R9A08G046_SDHI0_CLK_HS 43
> +#define R9A08G046_SDHI0_IACLKS 44
> +#define R9A08G046_SDHI0_IACLKM 45
> +#define R9A08G046_SDHI1_IMCLK 46
> +#define R9A08G046_SDHI1_IMCLK2 47
> +#define R9A08G046_SDHI1_CLK_HS 48
> +#define R9A08G046_SDHI1_IACLKS 49
> +#define R9A08G046_SDHI1_IACLKM 50
> +#define R9A08G046_SDHI2_IMCLK 51
> +#define R9A08G046_SDHI2_IMCLK2 52
> +#define R9A08G046_SDHI2_CLK_HS 53
> +#define R9A08G046_SDHI2_IACLKS 54
> +#define R9A08G046_SDHI2_IACLKM 55
> +#define R9A08G046_GE3D_CLK 56
> +#define R9A08G046_GE3D_AXI_CLK 57
> +#define R9A08G046_GE3D_ACE_CLK 58
> +#define R9A08G046_ISU_ACLK 59
> +#define R9A08G046_ISU_PCLK 60
> +#define R9A08G046_H264_CLK_A 61
> +#define R9A08G046_H264_CLK_P 62
> +#define R9A08G046_CRU_SYSCLK 63
> +#define R9A08G046_CRU_VCLK 64
> +#define R9A08G046_CRU_PCLK 65
> +#define R9A08G046_CRU_ACLK 66
> +#define R9A08G046_MIPI_DSI_PLLCLK 67

As per hardware manual this clock cannot be gated,
Looks this to be moved to core clk??
(4.4.6.4 Procedure for Activating the Modules Related to PLL7)

Cheers,
Biju