linux-next: manual merge of the amdgpu tree with the origin tree

[Mark Brown]

Hi all,

Today's linux-next merge of the amdgpu tree got a conflict in:

  drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

between commit:

  d25b32aa829a3 ("drm/amd/display: extend delta clamping logic to CM3 LUT helper")

from the origin tree and commits:

  0274a54897f35 ("drm/amd/display: extend delta clamping logic to CM3 LUT helper")
  92ff6a83cefeb ("drm/amd/display: Check return of shaper curve to HW format")

from the amdgpu tree.

I fixed it up (see below) and can carry the fix as necessary. This
is now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your tree
is submitted for merging.  You may also want to consider cooperating
with the maintainer of the conflicting tree to minimise any particularly
complex conflicts.

diff --combined drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
index 518794fad9e1f,a0aaa727e9fa3..0000000000000
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
@@@ -52,6 -52,7 +52,7 @@@
  #include "link_service.h"
  #include "../dcn20/dcn20_hwseq.h"
  #include "dc_state_priv.h"
+ #include "dio/dcn10/dcn10_dio.h"
  
  #define DC_LOGGER_INIT(logger)
  
@@@ -485,7 -486,7 +486,7 @@@ bool dcn32_set_mcm_luts
  	struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
  	int mpcc_id = pipe_ctx->plane_res.hubp->inst;
  	struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
- 	bool result = true;
+ 	bool rval, result;
  	const struct pwl_params *lut_params = NULL;
  
  	// 1D LUT
@@@ -508,10 -509,10 +509,10 @@@
  		lut_params = &plane_state->in_shaper_func.pwl;
  	else if (plane_state->in_shaper_func.type == TF_TYPE_DISTRIBUTED_POINTS) {
  		// TODO: dpp_base replace
- 		cm3_helper_translate_curve_to_hw_format(plane_state->ctx,
+ 		rval = cm3_helper_translate_curve_to_hw_format(plane_state->ctx,
  							&plane_state->in_shaper_func,
  							&dpp_base->shaper_params, true);
- 		lut_params = &dpp_base->shaper_params;
+ 		lut_params = rval ? &dpp_base->shaper_params : NULL;
  	}
  
  	mpc->funcs->program_shaper(mpc, lut_params, mpcc_id);
@@@ -957,13 -958,13 +958,13 @@@ void dcn32_init_hw(struct dc *dc
  	}
  
  	/* power AFMT HDMI memory TODO: may move to dis/en output save power*/
- 	REG_WRITE(DIO_MEM_PWR_CTRL, 0);
+ 	if (dc->res_pool->dio && dc->res_pool->dio->funcs->mem_pwr_ctrl)
+ 		dc->res_pool->dio->funcs->mem_pwr_ctrl(dc->res_pool->dio, false);
  
  	if (!dc->debug.disable_clock_gate) {
  		/* enable all DCN clock gating */
- 		REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
- 
- 		REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
+ 		if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->allow_clock_gating)
+ 			dc->res_pool->dccg->funcs->allow_clock_gating(dc->res_pool->dccg, true);
  
  		REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
  	}

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