Re: [PATCH] clk: sunxi-ng: sun55i-a523-r: Add missing r-spi module clock

[Andre Przywara]

On Tue, 17 Feb 2026 17:30:03 +0800
Chen-Yu Tsai <wens@xxxxxxxxxx> wrote:

Hi,

> When the PRCM clk driver was added, somehow the r-spi module clock
> was skipped over.
> 
> Add it so that r-spi can actually work.

The patch itself looks fine, compared against the manual, so for that:

Reviewed-by: Andre Przywara <andre.przywara@xxxxxxx>

But I noticed one thing below....

> Fixes: 8cea339cfb81 ("clk: sunxi-ng: add support for the A523/T527 PRCM CCU")
> Signed-off-by: Chen-Yu Tsai <wens@xxxxxxxxxx>
> ---
>  drivers/clk/sunxi-ng/ccu-sun55i-a523-r.c | 17 ++++++++++++++++-
>  1 file changed, 16 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/sunxi-ng/ccu-sun55i-a523-r.c b/drivers/clk/sunxi-ng/ccu-sun55i-a523-r.c
> index 0339c4af0fe5..db0e36d8838e 100644
> --- a/drivers/clk/sunxi-ng/ccu-sun55i-a523-r.c
> +++ b/drivers/clk/sunxi-ng/ccu-sun55i-a523-r.c
> @@ -83,9 +83,22 @@ static SUNXI_CCU_MUX_DATA_WITH_GATE(r_pwmctrl_clk, "r-pwmctrl",
>  static SUNXI_CCU_GATE_HW(bus_r_pwmctrl_clk, "bus-r-pwmctrl",
>  			 &r_apb0_clk.common.hw, 0x13c, BIT(0), 0);
>  
> -/* SPI clock is /M/N (same as new MMC?) */

Ooops, looks like I saw that clock, but someone managed to dodge it :-(
Sorry about that.

> +static const struct clk_parent_data r_spi_parents[] = {
> +	{ .fw_name = "hosc" },
> +	{ .fw_name = "pll-periph" },
> +	{ .name = "pll-periph0-300M" },
> +	{ .name = "pll-periph1-300M" },
> +	{ .name = "pll-audio" },

Looking a bit closer, all the PRCM PLL-AUDIO clocks in the manual refer to
AUDIO1PLL4X, which is provided by the MCU CCU, not AUDIO0PLL4X provided by
the main CCU. So we would need to change the DT? I wonder if that breaks
boots with kernels which didn't know the MCU CCU yet (v6.15-v6.17)?

Cheers,
Andre.

> +};
> +static SUNXI_CCU_DUALDIV_MUX_GATE(r_spi_clk, "r-spi", r_spi_parents, 0x150,
> +				  0, 5,		/* M */
> +				  8, 5,		/* P */
> +				  24, 3,	/* mux */
> +				  BIT(31),	/* gate */
> +				  0);
>  static SUNXI_CCU_GATE_HW(bus_r_spi_clk, "bus-r-spi",
>  			 &r_ahb_clk.common.hw, 0x15c, BIT(0), 0);
> +
>  static SUNXI_CCU_GATE_HW(bus_r_spinlock_clk, "bus-r-spinlock",
>  			 &r_ahb_clk.common.hw, 0x16c, BIT(0), 0);
>  static SUNXI_CCU_GATE_HW(bus_r_msgbox_clk, "bus-r-msgbox",
> @@ -138,6 +151,7 @@ static struct ccu_common *sun55i_a523_r_ccu_clks[] = {
>  	&bus_r_twd_clk.common,
>  	&r_pwmctrl_clk.common,
>  	&bus_r_pwmctrl_clk.common,
> +	&r_spi_clk.common,
>  	&bus_r_spi_clk.common,
>  	&bus_r_spinlock_clk.common,
>  	&bus_r_msgbox_clk.common,
> @@ -169,6 +183,7 @@ static struct clk_hw_onecell_data sun55i_a523_r_hw_clks = {
>  		[CLK_BUS_R_TWD]		= &bus_r_twd_clk.common.hw,
>  		[CLK_R_PWMCTRL]		= &r_pwmctrl_clk.common.hw,
>  		[CLK_BUS_R_PWMCTRL]	= &bus_r_pwmctrl_clk.common.hw,
> +		[CLK_R_SPI]		= &r_spi_clk.common.hw,
>  		[CLK_BUS_R_SPI]		= &bus_r_spi_clk.common.hw,
>  		[CLK_BUS_R_SPINLOCK]	= &bus_r_spinlock_clk.common.hw,
>  		[CLK_BUS_R_MSGBOX]	= &bus_r_msgbox_clk.common.hw,