Re: [PATCH 3/3] irqchip/irq-pruss-intc: Fix processing of IEP interrupts

From: Marc Zyngier

Date: Wed Feb 18 2026 - 06:05:08 EST


On Wed, 18 Feb 2026 07:08:45 +0000,
Meghana Malladi <m-malladi@xxxxxx> wrote:
>
> Hi Marc,
>
> On 9/19/23 13:02, Marc Zyngier wrote:
> > On Tue, 19 Sep 2023 07:19:00 +0100,
> > MD Danish Anwar <danishanwar@xxxxxx> wrote:
> >>
> >> From: Suman Anna <s-anna@xxxxxx>
> >>
> >> It was discovered that IEP capture/compare IRQs (event #7 on all SoCs
> >> and event #56 on K3 SoCs) are always triggered twice when PPS is
> >> generated and CMP hit event detected by IEP.
> >>
> >> An example of the problem is:
> >> pruss_intc_irq_handler
> >> generic_handle_irq
> >> handle_level_irq
> >> mask_ack_irq -> IRQ 7 masked and asked in INTC,
> >> but it's not yet cleared on HW level
> >> handle_irq_event()
> >> <threaded on RT>
> >> icss_iep_cap_cmp_handler() -> IRQ 7 is actually processed in HW
> >> irq_finalize_oneshot()
> >> unmask_irq()
> >> pruss_intc_irq_unmask() -> IRQ 7 status is still observed as set
> >>
> >> The solution is to actually ack these IRQs from pruss_intc_irq_unmask()
> >> after the IRQ source is cleared in HW.
> >
> > What you don't explain is whether the interrupt is level or edge
> > triggered? If it is level, then the "quirk" is that the interrupt
> > controller is slow to recognise that the level has changed. If it is
> > edge, this is a guaranteed recipe to lose interrupts.
> >
>
> These are level IRQs, but INTC has latency detecting the source
> deassertion, causing the double delivery (The hardware keeps the event
> asserted until cleared in IEP) - I will add more details about this
> fix in the commit message for v2.

I'm sorry, but this comes almost 3 years late, and I've long forgotten
about all of this. I can only conclude that if you (TI, not you
personally) waited for this long to address my comments, then this is
probably not something we really need to care about.

Thanks,

M.

--
Without deviation from the norm, progress is not possible.