Re: [PATCH] LoongArch: jump_label: Batch icache maintenance

[Huacai Chen]

Hi, Youling,

First of all, it is better to split to two patches:
LoongArch: Add flush_icache_all()/local_flush_icache_all()
LoongArch: Batch icache maintenance for jump_label


On Tue, Oct 28, 2025 at 2:53 PM Youling Tang <youling.tang@xxxxxxxxx> wrote:
>
> From: Youling Tang <tangyouling@xxxxxxxxxx>
>
> Switch to the batched version of the jump label update functions so
> instruction cache maintenance is deferred until the end of the update.
>
> Signed-off-by: Youling Tang <tangyouling@xxxxxxxxxx>
> ---
>  arch/loongarch/include/asm/cacheflush.h | 16 +++++++++++++++-
>  arch/loongarch/include/asm/jump_label.h |  1 +
>  arch/loongarch/kernel/inst.c            |  6 +++---
>  arch/loongarch/kernel/jump_label.c      | 13 +++++++++++--
>  arch/loongarch/mm/cache.c               | 10 ----------
>  5 files changed, 30 insertions(+), 16 deletions(-)
>
> diff --git a/arch/loongarch/include/asm/cacheflush.h b/arch/loongarch/include/asm/cacheflush.h
> index f8754d08a31a..66c34c821ecb 100644
> --- a/arch/loongarch/include/asm/cacheflush.h
> +++ b/arch/loongarch/include/asm/cacheflush.h
> @@ -31,9 +31,23 @@ static inline unsigned int cpu_last_level_cache_line_size(void)
>         return boot_cpu_data.cache_leaves[cache_present - 1].linesz;
>  }
>
> +/*
> + * LoongArch maintains ICache/DCache coherency by hardware,
> + * we just need "ibar" to avoid instruction hazard here.
> + */
> +static inline void local_flush_icache_all(void)
> +{
> +       asm volatile ("\tibar 0\n"::);
> +}
> +
> +static inline void local_flush_icache_range(unsigned long start, unsigned long end)
> +{
> +       local_flush_icache_all();
Just use a plain "asm volatile ("\tibar 0\n"::);", and put them after
__flush_cache_all().

Huacai

> +}
> +
>  asmlinkage void __flush_cache_all(void);
> -void local_flush_icache_range(unsigned long start, unsigned long end);
>
> +#define flush_icache_all       local_flush_icache_all
>  #define flush_icache_range     local_flush_icache_range
>  #define flush_icache_user_range        local_flush_icache_range
>
> diff --git a/arch/loongarch/include/asm/jump_label.h b/arch/loongarch/include/asm/jump_label.h
> index 4000c7603d8e..d0689032fd9d 100644
> --- a/arch/loongarch/include/asm/jump_label.h
> +++ b/arch/loongarch/include/asm/jump_label.h
> @@ -11,6 +11,7 @@
>
>  #include <linux/types.h>
>
> +#define HAVE_JUMP_LABEL_BATCH
>  #define JUMP_LABEL_NOP_SIZE    4
>
>  /* This macro is also expanded on the Rust side. */
> diff --git a/arch/loongarch/kernel/inst.c b/arch/loongarch/kernel/inst.c
> index bf037f0c6b26..65c1b74d677a 100644
> --- a/arch/loongarch/kernel/inst.c
> +++ b/arch/loongarch/kernel/inst.c
> @@ -209,6 +209,9 @@ int larch_insn_write(void *addr, u32 insn)
>         int ret;
>         unsigned long flags = 0;
>
> +       if ((unsigned long)addr & 3)
> +               return -EINVAL;
> +
>         raw_spin_lock_irqsave(&patch_lock, flags);
>         ret = copy_to_kernel_nofault(addr, &insn, LOONGARCH_INSN_SIZE);
>         raw_spin_unlock_irqrestore(&patch_lock, flags);
> @@ -221,9 +224,6 @@ int larch_insn_patch_text(void *addr, u32 insn)
>         int ret;
>         u32 *tp = addr;
>
> -       if ((unsigned long)tp & 3)
> -               return -EINVAL;
> -
>         ret = larch_insn_write(tp, insn);
>         if (!ret)
>                 flush_icache_range((unsigned long)tp,
> diff --git a/arch/loongarch/kernel/jump_label.c b/arch/loongarch/kernel/jump_label.c
> index 31891214b767..f5a394bdb5f3 100644
> --- a/arch/loongarch/kernel/jump_label.c
> +++ b/arch/loongarch/kernel/jump_label.c
> @@ -6,9 +6,11 @@
>   */
>  #include <linux/kernel.h>
>  #include <linux/jump_label.h>
> +#include <asm/cacheflush.h>
>  #include <asm/inst.h>
>
> -void arch_jump_label_transform(struct jump_entry *entry, enum jump_label_type type)
> +bool arch_jump_label_transform_queue(struct jump_entry *entry,
> +                                    enum jump_label_type type)
>  {
>         u32 insn;
>         void *addr = (void *)jump_entry_code(entry);
> @@ -18,5 +20,12 @@ void arch_jump_label_transform(struct jump_entry *entry, enum jump_label_type ty
>         else
>                 insn = larch_insn_gen_nop();
>
> -       larch_insn_patch_text(addr, insn);
> +       larch_insn_write(addr, insn);
> +
> +       return true;
> +}
> +
> +void arch_jump_label_transform_apply(void)
> +{
> +       flush_icache_all();
>  }
> diff --git a/arch/loongarch/mm/cache.c b/arch/loongarch/mm/cache.c
> index 6be04d36ca07..966b8d2b04ad 100644
> --- a/arch/loongarch/mm/cache.c
> +++ b/arch/loongarch/mm/cache.c
> @@ -31,16 +31,6 @@ void cache_error_setup(void)
>         set_merr_handler(0x0, &except_vec_cex, 0x80);
>  }
>
> -/*
> - * LoongArch maintains ICache/DCache coherency by hardware,
> - * we just need "ibar" to avoid instruction hazard here.
> - */
> -void local_flush_icache_range(unsigned long start, unsigned long end)
> -{
> -       asm volatile ("\tibar 0\n"::);
> -}
> -EXPORT_SYMBOL(local_flush_icache_range);
> -
>  static void flush_cache_leaf(unsigned int leaf)
>  {
>         int i, j, nr_nodes;
> --
> 2.43.0
>