Re: [PATCH] arm64: dts: qcom: qcm6490-idp: Enable PCIe1
From: Sushrut Shree Trivedi
Date: Thu Feb 19 2026 - 05:17:11 EST
On 2/12/2026 5:49 PM, Konrad Dybcio wrote:
On 2/12/26 1:06 PM, Sushrut Shree Trivedi wrote:The NVMe is actually soldered onto the board.
Remove PCIe1 clocks from protected-list and enable PCIe1 controllerIs that a M.2 slot? What key (B/M etc.)?
and its corresponding PHY nodes on qcm6490-idp platform.
PCIe1 is used to connect NVMe based SSD's on this platform.
If we de-assert the reset, it is an indication to the endpoint that it can participate
[...]
&pm7250b_gpios {You're asserting the active state of a pin permanently this way, unless
lcd_disp_bias_en: lcd-disp-bias-en-state {
pins = "gpio2";
@@ -920,6 +931,22 @@ &tlmm {
gpio-reserved-ranges = <32 2>, /* ADSP */
<48 4>; /* NFC */
+ pcie1_reset_n: pcie1-reset-n-state {
+ pins = "gpio2";
+ function = "gpio";
+ drive-strength = <16>;
+ output-low;
the driver takes over, please drop this line
in link-training with the host. Hence, until the host driver is probed and necessary
resources enabled, we keep the perst asserted so endpoint doesn't try to
participate in link training.
Ack'd.
+ bias-disable;Wrong indentation
+ };
Ack'd.
+Double \n
+ pcie1_wake_n: pcie1-wake-n-state {
+ pins = "gpio3";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+
sd_cd: sd-cd-state {
pins = "gpio91";
function = "gpio";
---
base-commit: 4f938c7d3b25d87b356af4106c2682caf8c835a2
change-id: 20260212-qcm6490-idp-24f7b6a1812d
Best regards,