Re: [PATCH v5 12/18] dt-bindings: dma: ti: Add K3 BCDMA V2

[Krzysztof Kozlowski]

On 19/02/2026 13:15, Sai Sree Kartheek Adivi wrote:
> 
> On 19/02/26 13:13, Krzysztof Kozlowski wrote:
> 
> Hi Krzysztof,
> 
> Thanks for the review.
>> On Wed, Feb 18, 2026 at 03:22:37PM +0530, Sai Sree Kartheek Adivi wrote:
>>> New binding document for
>> Fix wrapping - it's wrapped too early.
> Ack. will fix it in v6.
>>
>>> Texas Instruments K3 Block Copy DMA (BCDMA) V2.
>>>
>>> BCDMA V2 is introduced as part of AM62L.
>>>
>>> Signed-off-by: Sai Sree Kartheek Adivi <s-adivi@xxxxxx>
>>> ---
>>>   .../bindings/dma/ti/ti,am62l-dmss-bcdma.yaml  | 120 ++++++++++++++++++
>>>   1 file changed, 120 insertions(+)
>>>   create mode 100644 Documentation/devicetree/bindings/dma/ti/ti,am62l-dmss-bcdma.yaml
>>>
>>> diff --git a/Documentation/devicetree/bindings/dma/ti/ti,am62l-dmss-bcdma.yaml b/Documentation/devicetree/bindings/dma/ti/ti,am62l-dmss-bcdma.yaml
>>> new file mode 100644
>>> index 0000000000000..6fa08f22df375
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/dma/ti/ti,am62l-dmss-bcdma.yaml
>>> @@ -0,0 +1,120 @@
>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>> +# Copyright (C) 2024-25 Texas Instruments Incorporated
>>> +# Author: Sai Sree Kartheek Adivi <s-adivi@xxxxxx>
>>> +%YAML 1.2
>>> +---
>>> +$id: http://devicetree.org/schemas/dma/ti/ti,am62l-dmss-bcdma.yaml#
>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>> +
>>> +title: Texas Instruments K3 DMSS BCDMA V2
>>> +
>>> +maintainers:
>>> +  - Sai Sree Kartheek Adivi <s-adivi@xxxxxx>
>>> +
>>> +description:
>>> +  The BCDMA V2 is intended to perform similar functions as the TR
>>> +  mode channels of K3 UDMA-P.
>>> +  BCDMA V2 includes block copy channels and Split channels.
>>> +
>>> +  Block copy channels mainly used for memory to memory transfers, but with
>>> +  optional triggers a block copy channel can service peripherals by accessing
>>> +  directly to memory mapped registers or area.
>>> +
>>> +  Split channels can be used to service PSI-L based peripherals.
>>> +  The peripherals can be PSI-L native or legacy, non PSI-L native peripherals
>>> +  with PDMAs. PDMA is tasked to act as a bridge between the PSI-L fabric and the
>>> +  legacy peripheral.
>>> +
>>> +allOf:
>>> +  - $ref: /schemas/dma/dma-controller.yaml#
>>> +
>>> +properties:
>>> +  compatible:
>>> +    const: ti,am62l-dmss-bcdma
>>> +
>>> +  reg:
>>> +    items:
>>> +      - description: BCDMA Control & Status Registers region
>>> +      - description: Block Copy Channel Realtime Registers region
>>> +      - description: Channel Realtime Registers region
>>> +      - description: Ring Realtime Registers region
>>> +
>>> +  reg-names:
>>> +    items:
>>> +      - const: gcfg
>>> +      - const: bchanrt
>>> +      - const: chanrt
>>> +      - const: ringrt
>>> +
>>> +  "#address-cells":
>>> +    const: 0
>>> +
>>> +  "#interrupt-cells":
>>> +    const: 1
>> I don't get why this is nexus but not a interrupt-controller.
>>
>> Can you point me to DTS with complete picture using this?
> 
> Please refer 
> https://github.com/sskartheekadivi/linux/commit/4a7078a6892bfbc4c620b9668e3421b4c7405ca4
> 
> for the dt nodes of AM62L BCDMA and PKTDMA.
> 
> Refer to the below tree for full set of driver, dt-binding and dts changes
> 
> https://github.com/sskartheekadivi/linux/commits/dma-upstream-v5/

That's not complete. There are no consumers, so this does not really
answer my problem of lack of controller.

> 
>>
>>> +
>>> +  "#dma-cells":
>>> +    const: 4
>>> +    description: |
>>> +      cell 1: Trigger type for the channel
>>> +        0 - disable / no trigger
>>> +        1 - internal channel event
>>> +        2 - external signal
>>> +        3 - timer manager event
>>> +
>>> +      cell 2: parameter for the trigger:
>>> +        if cell 1 is 0 (disable / no trigger):
>>> +          Unused, ignored
>>> +        if cell 1 is 1 (internal channel event):
>>> +          channel number whose TR event should trigger the current channel.
>>> +        if cell 1 is 2 or 3 (external signal or timer manager event):
>>> +          index of global interfaces that come into the DMA.
>>> +
>>> +          Please refer to the device documentation for global interface indexes.
>>> +
>>> +      cell 3: Channel number for the peripheral
>>> +
>>> +        Please refer to the device documentation for the channel map.
>>> +
>>> +      cell 4: ASEL value for the channel
>>> +
>>> +  interrupt-map-mask:
>>> +    items:
>>> +      - const: 0x7ff
>>> +
>>> +  interrupt-map:
>>> +    description: |
>>> +      Maps internal BCDMA channel IDs to the parent GIC IRQ lines.
>> Isn't this mapping fixed in given device? IOW, not really part of DTS
>> description but deducible from the compatible.
>>
>> You only need to provide interrupts for your device.
> 
> I initially considered handling the mapping in the driver based on the
> 
> compatible string, but discussing the hardware architecture internally,
> 
> that approach becomes highly problematic for this IP block.
> 
> 
> While the mapping is fixed for the AM62L specifically, this same BCDMA V2
> 
> IP block is reused across different K3 SoCs, and the internal
> 
> channel-to-IRQ wiring changes entirely from SoC to SoC. Furthermore, the
> 
> mapping of internal channels to the parent GIC interrupts is discontiguous
> 
> (and the hardware IP itself supports mapping multiple DMA channels to a
> 
> single shared IRQ line, depending on the SoC integration).
> 
> 
> If we rely on the driver to deduce this via the compatible string, we will
> 
> have to maintain large, discontiguous mapping tables inside the driver
> 
> code for every new SoC that integrates this IP.

And why maintaining exactly same mapping in DTS is okay? What's entirely
deducible from the compatible does not belong to the DTS.

> 
> 
> Because the IP is essentially routing its internal channel events to a
> 
> different set of parent IRQs (which varies per SoC integration), using
> 
> interrupt-map allows us to accurately describe the specific SoC's wiring
> 
> purely in the DT. This keeps the driver clean and easily reusable for
> 
> future K3 SoCs without creeping hardware routing tables into the driver
> 
> code.


All of this is difficult to read. Fix your email client please. I just
skimmed through it, not going to force my brain to work with broken
formatting. Make it easy for reviewers to discuss your patches... if
not, then silence and no ack.

Best regards,
Krzysztof