Re: [PATCH net-next v2] net: phy: micrel: Add support for lan9645x internal phy

[Russell King (Oracle)]

On Fri, Feb 20, 2026 at 10:30:36PM +0100, Heiner Kallweit wrote:
> On 20.02.2026 22:10, Russell King (Oracle) wrote:
> > On Fri, Feb 20, 2026 at 09:50:44PM +0100, Heiner Kallweit wrote:
> >> No, BMCR_RESET usually doesn't reset configuration registers. That's why the
> >> function is called genphy_*soft*_reset. In case your PHY behaves different,
> >> which configuration registers does it change?
> > 
> > I don't think your statement is correct.
> > 
> > Looking at AR8035 for example, the WoL interrupt enable is doumented as
> > being cleared on soft reset. Smart Speed configuration also gets reset.
> > 
> > 802.3 22.2.4.1.1 states that setting 0.15 results in the status and
> > control registers shall be set to their default states.
> > 
> > So, we should not assume that setting 0.15 will retain configuration in
> > the PHY - at least phylib should not assume that a call to
> > genphy_soft_reset will not clear the configuration registers. If we
> > have code in phylib that makes that assumption, phylib is buggy to
> > 802.3.
> > 
> 
> Indeed I was wondering why c22 states "reset control registers"
> whilst the PHY's I'm dealing with don't do this. At least for the
> Marvell PHY's I used the spec says "resets PHY state machine".
> For Realtek the spec statement was "resets BMCR and BMSR".
> And often config bits are described as "becomes effective after
> reset". But yes, there may be PHY's implementing exactly the c22
> behavior, so we shouldn't rely on "soft" in general.

Looking at LAN8841
(https://ww1.microchip.com/downloads/aemDocuments/documents/UNG/ProductDocuments/DataSheets/LAN8841-Data-Sheet-00004726A.pdf)
this states:

5.28.1 SOFTWARE RESET
The Gigabit Ethernet PHY may be reset by software by using the IEEE
802.3 standard PHY Soft Reset (RESET) bit in the Basic Control
Register. This resets all the PHY and all its registers to their
default state, with the following exceptions.

(none mention standard 802.3 registers)

An additional software reset is available by using the bit Software
Reset bit in the Control Register. This resets all of the PHY except
for its registers.

So, setting 0.15 will be disruptive to the control registers on this
PHY. Register definitions can be found at:
https://ww1.microchip.com/downloads/aemDocuments/documents/UNG/ApplicationNotes/ApplicationNotes/AN4783-LAN8841-Register-Definitions-Application-Note-DS00004783A.pdf

Bit 1 of register 31 resets the PHY without clearing the registers.

As one of their PHYs behaves like this, I suspect it'll be common
amongst their LAN PHYs. The KSZ PHYs seem to either be more like
Marvell, or maybe the documentation isn't clear enough.

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