[PATCH 2/2] Revert "drm/amd/pm: Disable SCLK switching on Oland with high pixel clocks (v3)"

[Rosen Penev]

This reverts commit 0bb91bed82d414447f2e56030d918def6383c026.

This commit breaks stable kernels older than 6.18 that are booted with
radeon.si_support=0 amdgpu.si_support=1 amdgpu.dc=1

In 6.17, threre are further commits that are needed to get the DC
codepath in amdgpu for Southern Islands GPUs working but they seem to be
too much of a hastle to backport cleanly. The simplest solution is to
revert this problematic commit

Cc: Timur Kristóf <timur.kristof@xxxxxxxxx>
Cc: Alex Deucher <alexander.deucher@xxxxxxx>
Signed-off-by: Rosen Penev <rosenp@xxxxxxxxx>
---
 drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c | 31 ----------------------
 1 file changed, 31 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
index 05eaa06dfa34..c4386c86153b 100644
--- a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
+++ b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
@@ -3426,14 +3426,12 @@ static void si_apply_state_adjust_rules(struct amdgpu_device *adev,
 {
 	struct  si_ps *ps = si_get_ps(rps);
 	struct amdgpu_clock_and_voltage_limits *max_limits;
-	struct amdgpu_connector *conn;
 	bool disable_mclk_switching = false;
 	bool disable_sclk_switching = false;
 	u32 mclk, sclk;
 	u16 vddc, vddci, min_vce_voltage = 0;
 	u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;
 	u32 max_sclk = 0, max_mclk = 0;
-	u32 high_pixelclock_count = 0;
 	int i;
 
 	if (adev->asic_type == CHIP_HAINAN) {
@@ -3466,35 +3464,6 @@ static void si_apply_state_adjust_rules(struct amdgpu_device *adev,
 		}
 	}
 
-	/* We define "high pixelclock" for SI as higher than necessary for 4K 30Hz.
-	 * For example, 4K 60Hz and 1080p 144Hz fall into this category.
-	 * Find number of such displays connected.
-	 */
-	for (i = 0; i < adev->mode_info.num_crtc; i++) {
-		if (!(adev->pm.dpm.new_active_crtcs & (1 << i)) ||
-			!adev->mode_info.crtcs[i]->enabled)
-			continue;
-
-		conn = to_amdgpu_connector(adev->mode_info.crtcs[i]->connector);
-
-		if (conn->pixelclock_for_modeset > 297000)
-			high_pixelclock_count++;
-	}
-
-	/* These are some ad-hoc fixes to some issues observed with SI GPUs.
-	 * They are necessary because we don't have something like dce_calcs
-	 * for these GPUs to calculate bandwidth requirements.
-	 */
-	if (high_pixelclock_count) {
-		/* On Oland, we observe some flickering when two 4K 60Hz
-		 * displays are connected, possibly because voltage is too low.
-		 * Raise the voltage by requiring a higher SCLK.
-		 * (Voltage cannot be adjusted independently without also SCLK.)
-		 */
-		if (high_pixelclock_count > 1 && adev->asic_type == CHIP_OLAND)
-			disable_sclk_switching = true;
-	}
-
 	if (rps->vce_active) {
 		rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk;
 		rps->ecclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].ecclk;
-- 
2.53.0