Re: [PATCH v3 3/3] arm64: dts: qcom: sm8750: Add GPU clock & IOMMU nodes
From: Akhil P Oommen
Date: Sat Feb 21 2026 - 13:23:05 EST
On 2/20/2026 11:24 AM, Taniya Das wrote:
> From: Konrad Dybcio <konrad.dybcio@xxxxxxxxxxxxxxxx>
>
> Add the GPU_CC and GX_CC (brand new! as far as we're concerned, this
> is simply a separate block housing the GX GDSC) nodes, required to
> power up the graphics-related hardware.
>
> Make use of it by enabling the associated IOMMU as well. The GPU itself
> needs some more work and will be enabled later.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxxxxxxxx>
> Co-developed-by: Taniya Das <taniya.das@xxxxxxxxxxxxxxxx>
> Signed-off-by: Taniya Das <taniya.das@xxxxxxxxxxxxxxxx>
> ---
> arch/arm64/boot/dts/qcom/sm8750.dtsi | 64 ++++++++++++++++++++++++++++++++++++
> 1 file changed, 64 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi
> index f56b1f889b857a28859910f5c4465c8ce3473b00..0cc931d0bc96e9563ce4e7989ecd4ba50bd424f8 100644
> --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi
> @@ -4,7 +4,9 @@
> */
>
> #include <dt-bindings/clock/qcom,rpmh.h>
> +#include <dt-bindings/clock/qcom,kaanapali-gxclkctl.h>
> #include <dt-bindings/clock/qcom,sm8750-gcc.h>
> +#include <dt-bindings/clock/qcom,sm8750-gpucc.h>
> #include <dt-bindings/clock/qcom,sm8750-tcsr.h>
> #include <dt-bindings/clock/qcom,sm8750-videocc.h>
> #include <dt-bindings/dma/qcom-gpi.h>
> @@ -3001,6 +3003,30 @@ videocc: clock-controller@aaf0000 {
> #power-domain-cells = <1>;
> };
>
> + gxclkctl: clock-controller@3d64000 {
> + compatible = "qcom,sm8750-gxclkctl";
> + reg = <0x0 0x03d64000 0x0 0x6000>;
> +
> + power-domains = <&rpmhpd RPMHPD_GFX>,
> + <&rpmhpd RPMHPD_GMXC>,
> + <&gpucc GPU_CC_CX_GDSC>;
> +
> + #power-domain-cells = <1>;
> + };
> +
> + gpucc: clock-controller@3d90000 {
> + compatible = "qcom,sm8750-gpucc";
> + reg = <0x0 0x03d90000 0x0 0x9800>;
> +
> + clocks = <&bi_tcxo_div2>,
> + <&gcc GCC_GPU_GPLL0_CLK_SRC>,
> + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
> +
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + #power-domain-cells = <1>;
On Pakala and newer GPUs, we need to scale GMU (which is connected to
the CX GDSC) freq. Is this DT description sufficient to allow scaling of
GMU OPP?
-Akhil.
> + };
> +
> pdc: interrupt-controller@b220000 {
> compatible = "qcom,sm8750-pdc", "qcom,pdc";
> reg = <0x0 0x0b220000 0x0 0x10000>, <0x0 0x164400f0 0x0 0x64>;
> @@ -4515,6 +4541,44 @@ tpdm_swao_out: endpoint {
> };
> };
>
> + adreno_smmu: iommu@3da0000 {
> + compatible = "qcom,sm8750-smmu-500", "qcom,adreno-smmu",
> + "qcom,smmu-500", "arm,mmu-500";
> + reg = <0x0 0x03da0000 0x0 0x40000>;
> + #iommu-cells = <2>;
> + #global-interrupts = <1>;
> + interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 660 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 667 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 670 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 700 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
> + clock-names = "hlos";
> + power-domains = <&gpucc GPU_CC_CX_GDSC>;
> + dma-coherent;
> + };
> +
> apps_smmu: iommu@15000000 {
> compatible = "qcom,sm8750-smmu-500", "qcom,smmu-500", "arm,mmu-500";
> reg = <0x0 0x15000000 0x0 0x100000>;
>