Re: [PATCH v2 1/1] arm64: dts: qcom: monaco-evk: Add Interface Plus Mezzanine

From: Dmitry Baryshkov

Date: Sun Feb 22 2026 - 13:28:10 EST

On Sun, Feb 22, 2026 at 11:05:45PM +0530, Umang Chheda wrote:
> The Interface Plus [IFP] Mezzanine is an hardware expansion add-on
> board designed to be stacked on top of Monaco EVK.
>
> It has following peripherals :
>
> - 4x Type A USB ports in host mode.
> - TC9563 PCIe switch, which has following three downstream ports (DSP) :
> - 1st DSP connects M.2 E-key connector for connecting WLAN endpoints.

Nit: routed to? Is that M.2 only suitable for WLANs? What is "WLAN
endpoints"?

> - 2nd DSP connects M.2 B-key connector for connecting cellular
> modems.
> - 3rd DSP with support for Dual Ethernet ports.
> - EEPROM.
> - LVDS Display.
> - 2*mini DP.
>
> Add support for following peripherals :
> - TC9563 PCIe Switch.
> - EEPROM.

If there is an onboard USB hub, please describe it here. Also, what is
the story of mini DP ports? If they are to be enabled later, please
mention, why.

>
> Written with inputs from :
> Krishna Chaitanya Chundru <krishna.chundru@xxxxxxxxxxxxxxxx> - PCIe
> Monish Chunara <monish.chunara@xxxxxxxxxxxxxxxx> - EEPROM.
>
> Signed-off-by: Umang Chheda <umang.chheda@xxxxxxxxxxxxxxxx>
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxxxxxxxx>
> ---
> arch/arm64/boot/dts/qcom/Makefile | 4 +
> .../dts/qcom/monaco-evk-ifp-mezzanine.dtso | 184 ++++++++++++++++++
> 2 files changed, 188 insertions(+)
> create mode 100644 arch/arm64/boot/dts/qcom/monaco-evk-ifp-mezzanine.dtso
>
> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
> index f80b5d9cf1e8..9d298e7e8a90 100644
> --- a/arch/arm64/boot/dts/qcom/Makefile
> +++ b/arch/arm64/boot/dts/qcom/Makefile
> @@ -45,6 +45,10 @@ lemans-evk-el2-dtbs := lemans-evk.dtb lemans-el2.dtbo
> dtb-$(CONFIG_ARCH_QCOM) += lemans-evk-el2.dtb
> dtb-$(CONFIG_ARCH_QCOM) += milos-fairphone-fp6.dtb
> dtb-$(CONFIG_ARCH_QCOM) += monaco-evk.dtb
> +
> +monaco-evk-ifp-mezzanine-dtbs := monaco-evk.dtb monaco-evk-ifp-mezzanine.dtbo
> +
> +dtb-$(CONFIG_ARCH_QCOM) += monaco-evk-ifp-mezzanine.dtb
> dtb-$(CONFIG_ARCH_QCOM) += msm8216-samsung-fortuna3g.dtb
> dtb-$(CONFIG_ARCH_QCOM) += msm8916-acer-a1-724.dtb
> dtb-$(CONFIG_ARCH_QCOM) += msm8916-alcatel-idol347.dtb
> diff --git a/arch/arm64/boot/dts/qcom/monaco-evk-ifp-mezzanine.dtso b/arch/arm64/boot/dts/qcom/monaco-evk-ifp-mezzanine.dtso
> new file mode 100644
> index 000000000000..f0572647200c
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/monaco-evk-ifp-mezzanine.dtso
> @@ -0,0 +1,184 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
> + */
> +
> +/dts-v1/;
> +/plugin/;
> +
> +#include <dt-bindings/gpio/gpio.h>
> +
> +&{/} {
> + model = "Qualcomm Technologies, Inc. Monaco-EVK IFP Mezzanine";
> +
> + vreg_0p9: regulator-vreg-0p9 {

Are all these regulators a part of the mezzanine?

> + compatible = "regulator-fixed";
> + regulator-name = "VREG_0P9";
> +
> + regulator-min-microvolt = <900000>;
> + regulator-max-microvolt = <900000>;
> + regulator-always-on;
> + regulator-boot-on;
> +
> + vin-supply = <&vreg_3p3>;
> + };
> +
> + vreg_1p8: regulator-vreg-1p8 {
> + compatible = "regulator-fixed";
> + regulator-name = "VREG_1P8";
> +
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-always-on;
> + regulator-boot-on;
> +
> + vin-supply = <&vreg_4p2>;
> + };
> +
> + vreg_3p3: regulator-vreg-3p3 {
> + compatible = "regulator-fixed";
> + regulator-name = "VREG_3P3";
> +
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + regulator-boot-on;
> +
> + vin-supply = <&vreg_4p2>;
> + };
> +
> + vreg_4p2: regulator-vreg-4p2 {
> + compatible = "regulator-fixed";
> + regulator-name = "VREG_4P2";
> +
> + regulator-min-microvolt = <4200000>;
> + regulator-max-microvolt = <4200000>;
> + regulator-always-on;
> + regulator-boot-on;
> +
> + vin-supply = <&vreg_sys_pwr>;
> + };
> +
> + vreg_sys_pwr: regulator-vreg-sys-pwr {
> + compatible = "regulator-fixed";
> + regulator-name = "VREG_SYS_PWR";
> +
> + regulator-min-microvolt = <24000000>;
> + regulator-max-microvolt = <24000000>;
> + regulator-always-on;
> + regulator-boot-on;

... supplied from what?

> + };
> +};
> +
> +&i2c15 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + eeprom1: eeprom@52 {
> + compatible = "giantec,gt24c256c", "atmel,24c256";
> + reg = <0x52>;
> + pagesize = <64>;
> +
> + nvmem-layout {
> + compatible = "fixed-layout";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + };
> + };
> +};
> +
> +&pcie0 {
> + iommu-map = <0x0 &pcie_smmu 0x0 0x1>,
> + <0x100 &pcie_smmu 0x1 0x1>,
> + <0x208 &pcie_smmu 0x2 0x1>,
> + <0x210 &pcie_smmu 0x3 0x1>,
> + <0x218 &pcie_smmu 0x4 0x1>,
> + <0x300 &pcie_smmu 0x5 0x1>,
> + <0x400 &pcie_smmu 0x6 0x1>,
> + <0x500 &pcie_smmu 0x7 0x1>,
> + <0x501 &pcie_smmu 0x8 0x1>;
> +};
> +
> +&pcieport0 {
> + #address-cells = <3>;
> + #size-cells = <2>;
> +
> + pcie@0,0 {
> + compatible = "pci1179,0623";
> + reg = <0x10000 0x0 0x0 0x0 0x0>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> +
> + device_type = "pci";
> + ranges;
> + bus-range = <0x2 0xff>;
> +
> + vddc-supply = <&vreg_0p9>;
> + vdd18-supply = <&vreg_1p8>;
> + vdd09-supply = <&vreg_0p9>;
> + vddio1-supply = <&vreg_1p8>;
> + vddio2-supply = <&vreg_1p8>;
> + vddio18-supply = <&vreg_1p8>;
> +
> + i2c-parent = <&i2c15 0x77>;
> +
> + resx-gpios = <&tlmm 124 GPIO_ACTIVE_LOW>;
> +
> + pinctrl-0 = <&tc9563_resx_n>;
> + pinctrl-names = "default";
> +
> + pcie@1,0 {
> + reg = <0x20800 0x0 0x0 0x0 0x0>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> +
> + device_type = "pci";
> + ranges;
> + bus-range = <0x3 0xff>;
> + };
> +
> + pcie@2,0 {
> + reg = <0x21000 0x0 0x0 0x0 0x0>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> +
> + device_type = "pci";
> + ranges;
> + bus-range = <0x4 0xff>;
> + };
> +
> + pcie@3,0 {
> + reg = <0x21800 0x0 0x0 0x0 0x0>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> + device_type = "pci";
> + ranges;
> + bus-range = <0x5 0xff>;
> +
> + pci@0,0 {
> + reg = <0x50000 0x0 0x0 0x0 0x0>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> + device_type = "pci";
> + ranges;
> + };
> +
> + pci@0,1 {
> + reg = <0x50100 0x0 0x0 0x0 0x0>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> + device_type = "pci";
> + ranges;
> + };
> + };
> + };
> +};
> +
> +&tlmm {
> + tc9563_resx_n: tc9563-resx-state {
> + pins = "gpio124";
> + function = "gpio";
> + bias-disable;
> + output-high;
> + };
> +};
> --
> 2.34.1
>

--
With best wishes
Dmitry