Re: [PATCH 1/3] clk: microchip: core: update to use div64_ul() instead of do_div()
From: David Laight
Date: Mon Feb 23 2026 - 04:20:05 EST
On Sun, 22 Feb 2026 18:51:04 -0500
Brian Masney <bmasney@xxxxxxxxxx> wrote:
> This driver is currently only compiled on 32-bit MIPS systems. When
> compiling on 64-bit systems, the build fails with:
>
> WARNING: do_div() does a 64-by-32 division, please consider using
> div64_ul instead.
>
> Let's update this to use div64_ul() in preparation for allowing this
> driver to be compiled on all architectures.
There are a log of 'long' in that code that hold clock frequencies.
I suspect they should be u32 (I think someone was scared that int might be 16bit).
>
> Reported-by: kernel test robot <lkp@xxxxxxxxx>
> Closes: https://lore.kernel.org/oe-kbuild-all/202601160758.bpkN4546-lkp@xxxxxxxxx/
> Signed-off-by: Brian Masney <bmasney@xxxxxxxxxx>
> ---
> drivers/clk/microchip/clk-core.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/microchip/clk-core.c b/drivers/clk/microchip/clk-core.c
> index 692152b5094e00bf5acb19a67cf41e6c86b11f35..2e86ad846a66cd5487f5412c09ab0ad25ebe3f79 100644
> --- a/drivers/clk/microchip/clk-core.c
> +++ b/drivers/clk/microchip/clk-core.c
> @@ -341,7 +341,7 @@ static void roclk_calc_div_trim(unsigned long rate,
> div = parent_rate / (rate << 1);
> frac = parent_rate;
> frac <<= 8;
> - do_div(frac, rate);
> + frac = div64_ul(frac, rate);
> frac -= (u64)(div << 9);
Is that cast in the right place?
I suspect 'div' can't be large enough to need it, but it's presence makes
my wonder ...
David
>
> rodiv = (div > REFO_DIV_MASK) ? REFO_DIV_MASK : div;
>