Re: [PATCH] EDAC/versalnet: Fix resource leaks and NULL derefs in init_versalnet()

[Eric_Terminal]

On Mon, Feb 23, 2026 at 9:47 PM Borislav Petkov <bp@xxxxxxxxx> wrote:
> And I'd usually say you can take the current diffs, productize them and send them after testing.

Uh, yeah, that’s true — after all, most of us regular developers don’t
exactly have an FPGA sitting around at home.

> However, testing is the problem here - I highly doubt you have access to the hardware and Shubhrajyoti is probably one of small number of people who can test it.

This is purely a logic bug in the code. What I did was just fix an
error-handling path; it doesn’t change the normal execution flow at
all. The issue itself can be derived through static analysis of the
existing code, so it’s not something that depends on specific hardware
behavior.

> Except that he's not really moving here - this particular issue has been outstanding for at least three months.

If the driver isn’t actively maintained… well… I can understand that
too. Still, this patch is very low risk, and merging it shouldn’t
really add to your workload. Maybe straightforward logic fixes like
this could be considered based on static review alone? At the very
least, it would help improve the baseline code quality. :)

Anyway, enjoy your vacation.