Re: [PATCH v2 3/5] arm64: dts: qcom: agatti: add LPASS devices
From: Dmitry Baryshkov
Date: Mon Feb 23 2026 - 21:59:13 EST
On Mon, Feb 23, 2026 at 01:39:48PM +0000, Srinivas Kandagatla wrote:
> From: Alexey Klimov <alexey.klimov@xxxxxxxxxx>
>
> The rxmacro, txmacro, vamacro, soundwire nodes, lpass clock
> controllers are required to support audio playback and
> audio capture on sm6115 and its derivatives.
>
> Signed-off-by: Alexey Klimov <alexey.klimov@xxxxxxxxxx>
> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@xxxxxxxxxxxxxxxx>
> ---
> arch/arm64/boot/dts/qcom/agatti.dtsi | 167 +++++++++++++++++++++++++++
> 1 file changed, 167 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/agatti.dtsi b/arch/arm64/boot/dts/qcom/agatti.dtsi
> index 76b93b7bd50f..e59a1a87ee0a 100644
> --- a/arch/arm64/boot/dts/qcom/agatti.dtsi
> +++ b/arch/arm64/boot/dts/qcom/agatti.dtsi
> @@ -758,6 +758,42 @@ data-pins {
> drive-strength = <8>;
> };
> };
> +
> + lpass_tx_swr_active: lpass-tx-swr-active-state {
> + clk-pins {
> + pins = "gpio0";
> + function = "swr_tx_clk";
> + drive-strength = <10>;
> + slew-rate = <3>;
> + bias-disable;
> + };
> +
> + data-pins {
> + pins = "gpio1", "gpio2";
> + function = "swr_tx_data";
> + drive-strength = <10>;
> + slew-rate = <3>;
> + bias-bus-hold;
> + };
> + };
> +
> + lpass_rx_swr_active: lpass-rx-swr-active-state {
> + clk-pins {
> + pins = "gpio3";
> + function = "swr_rx_clk";
> + drive-strength = <10>;
> + slew-rate = <3>;
> + bias-disable;
> + };
> +
> + data-pins {
> + pins = "gpio4", "gpio5";
> + function = "swr_rx_data";
> + drive-strength = <10>;
> + slew-rate = <3>;
> + bias-bus-hold;
> + };
> + };
> };
>
> gcc: clock-controller@1400000 {
> @@ -2188,6 +2224,137 @@ glink-edge {
> };
> };
>
> + rxmacro: codec@a600000 {
> + compatible = "qcom,sm6115-lpass-rx-macro";
> + reg = <0x0 0xa600000 0x0 0x1000>;
> +
> + clocks = <&q6afecc LPASS_CLK_ID_RX_CORE_MCLK
> + LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
> + <&q6afecc LPASS_CLK_ID_RX_CORE_NPL_MCLK
> + LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
> + <&q6afecc LPASS_HW_DCODEC_VOTE
> + LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
> + <&vamacro>;
> + clock-names = "mclk",
> + "npl",
> + "dcodec",
> + "fsgen";
> + #clock-cells = <0>;
> + clock-output-names = "mclk";
> + #sound-dai-cells = <1>;
> + };
> +
> + swr1: soundwire@a610000 {
> + compatible = "qcom,soundwire-v1.6.0";
> + reg = <0x0 0x0a610000 0x0 0x10000>;
> + interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
> +
> + clocks = <&rxmacro>;
> + clock-names = "iface";
> +
> + resets = <&lpass_audiocc 0>;
> + reset-names = "swr_audio_cgcr";
> +
> + label = "RX";
> + qcom,din-ports = <0>;
> + qcom,dout-ports = <5>;
> +
> + qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;
> + qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>;
> + qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;
> + qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
> + qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
> + qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
> + qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
> + qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
> + qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
> +
> + #sound-dai-cells = <1>;
> + #address-cells = <2>;
> + #size-cells = <0>;
> + };
> +
> +
Double empty line
> + txmacro: codec@a620000 {
> + compatible = "qcom,sm6115-lpass-tx-macro";
> + reg = <0x0 0x0a620000 0x0 0x1000>;
> +
> + clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK
> + LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
Please adjust indentation (the most logical would be to put the whole
clock definition to a single line.
> + <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK
> + LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
> + <&q6afecc LPASS_HW_DCODEC_VOTE
> + LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
> + <&vamacro>;
> + clock-names = "mclk",
> + "npl",
> + "dcodec",
> + "fsgen";
> + #clock-cells = <0>;
> + clock-output-names = "mclk";
> + #sound-dai-cells = <1>;
> + };
> +
> + lpass_audiocc: clock-controller@a6a9000 {
> + compatible = "qcom,sm6115-lpassaudiocc";
> + reg = <0x0 0x0a6a9000 0x0 0x1000>;
> + #reset-cells = <1>;
> + };
> +
> + vamacro: codec@a730000 {
> + compatible = "qcom,sm6115-lpass-va-macro";
> + reg = <0x0 0x0a730000 0x0 0x1000>;
> +
> + clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK
> + LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
The same
> + <&q6afecc LPASS_HW_DCODEC_VOTE
> + LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
> + <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK
> + LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
> + clock-names = "mclk",
> + "dcodec",
> + "npl";
> + #clock-cells = <0>;
> + clock-output-names = "fsgen";
> + #sound-dai-cells = <1>;
> + };
> +
> + swr0: soundwire@a740000 {
> + compatible = "qcom,soundwire-v1.6.0";
> + reg = <0x0 0x0a740000 0x0 0x10000>;
> + interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&txmacro>;
> + clock-names = "iface";
> +
> + resets = <&lpasscc 0>;
> + reset-names = "swr_audio_cgcr";
> +
> + label = "VA_TX";
> + qcom,din-ports = <3>;
> + qcom,dout-ports = <0>;
> +
> + qcom,ports-sinterval-low = /bits/ 8 <0x03 0x03 0x03>;
> + qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x01>;
> + qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00>;
> + qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff>;
> + qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff>;
> + qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff>;
> + qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff>;
> + qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff>;
> + qcom,ports-lane-control = /bits/ 8 <0x00 0x00 0x00>;
> +
> + #sound-dai-cells = <1>;
> + #address-cells = <2>;
> + #size-cells = <0>;
> + };
> +
> + lpasscc: clock-controller@a7ec000 {
> + compatible = "qcom,sm6115-lpasscc";
> + reg = <0x0 0x0a7e0000 0x0 0x12000>;
> + #reset-cells = <1>;
> + };
> +
> remoteproc_adsp: remoteproc@ab00000 {
> compatible = "qcom,qcm2290-adsp-pas", "qcom,sm6115-adsp-pas";
> reg = <0x0 0x0ab00000 0x0 0x100>;
> --
> 2.47.3
>
--
With best wishes
Dmitry