Re: [PATCH 5/8] dmaengine: tegra: Support address width > 40 bits

[Akhil R]

On Tue, 17 Feb 2026 14:44:28 -0500 Frank Li wrote:
> On Tue, Feb 17, 2026 at 11:04:54PM +0530, Akhil R wrote:
>> Tegra264 supports address width of 41 bits and has a separate register
>> to accommodate the high address. Add a device data property to specify
>> the number of address bits supported on a device and use that to
>> program the required registers.
>>
>> Signed-off-by: Akhil R <akhilrajeev@xxxxxxxxxx>
>> ---
>>  drivers/dma/tegra186-gpc-dma.c | 129 +++++++++++++++++++++------------
>>  1 file changed, 82 insertions(+), 47 deletions(-)
>>
>> diff --git a/drivers/dma/tegra186-gpc-dma.c b/drivers/dma/tegra186-gpc-dma.c
>> index 72701b543ceb..ce3b1dd52bb3 100644
>> --- a/drivers/dma/tegra186-gpc-dma.c
>> +++ b/drivers/dma/tegra186-gpc-dma.c
>> @@ -151,6 +151,7 @@ struct tegra_dma_channel;
>>   */
>>  struct tegra_dma_chip_data {
>>  	bool hw_support_pause;
>> +	unsigned int addr_bits;
>>  	unsigned int nr_channels;
>>  	unsigned int channel_reg_size;
>>  	unsigned int max_dma_count;
>> @@ -166,6 +167,8 @@ struct tegra_dma_channel_regs {
>>  	u32 src;
>>  	u32 dst;
>>  	u32 high_addr;
>> +	u32 src_high;
>> +	u32 dst_high;
>>  	u32 mc_seq;
>>  	u32 mmio_seq;
>>  	u32 wcount;
>> @@ -189,7 +192,8 @@ struct tegra_dma_sg_req {
>>  	u32 csr;
>>  	u32 src;
>>  	u32 dst;
>> -	u32 high_addr;
>> +	u32 src_high;
>> +	u32 dst_high;
>>  	u32 mc_seq;
>>  	u32 mmio_seq;
>>  	u32 wcount;
>> @@ -273,6 +277,41 @@ static inline struct device *tdc2dev(struct tegra_dma_channel *tdc)
>>  	return tdc->vc.chan.device->dev;
>>  }
>>
>> +static void tegra_dma_program_addr(struct tegra_dma_channel *tdc,
>> +				   struct tegra_dma_sg_req *sg_req)
>> +{
>> +	tdc_write(tdc, tdc->regs->src, sg_req->src);
>> +	tdc_write(tdc, tdc->regs->dst, sg_req->dst);
>> +
>> +	if (tdc->tdma->chip_data->addr_bits > 40) {
>> +		tdc_write(tdc, tdc->regs->src_high,
>> +			  sg_req->src_high);
>> +		tdc_write(tdc, tdc->regs->dst_high,
>> +			  sg_req->dst_high);
>> +	} else {
>> +		tdc_write(tdc, tdc->regs->high_addr,
>> +			  sg_req->src_high | sg_req->dst_high);
>> +	}
>> +}
>> +
>> +static void tegra_dma_configure_addr(struct tegra_dma_channel *tdc,
>> +				     struct tegra_dma_sg_req *sg_req,
>> +				phys_addr_t src, phys_addr_t dst)
>> +{
>> +	sg_req->src = lower_32_bits(src);
>> +	sg_req->dst = lower_32_bits(dst);
> 
> I suggest save 64bit address to sq_req.  In tegra_dma_program_addr() to
> handle difference between 40bit and 41bit.
> 
> So only need handle difference at one place.

Ack. Will update. 

Regards,
Akhil