Re: [PATCH v3 5/5] dt-bindings: arm: atmel,at91rm9200-sdramc: convert to DT schema

From: Conor Dooley

Date: Thu Feb 26 2026 - 13:54:33 EST


On Thu, Feb 26, 2026 at 04:13:37PM +0000, Akhila YS wrote:
> Convert RAMC SDRAM/DDR controller binding to YAML format.
>
> Signed-off-by: Akhila YS <akhilayalmati@xxxxxxxxx>
> ---
> .../bindings/arm/atmel,at91rm9200-sdramc.yaml | 67 ++++++++++++++++++++++
> .../devicetree/bindings/arm/atmel-sysregs.txt | 20 -------
> 2 files changed, 67 insertions(+), 20 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/arm/atmel,at91rm9200-sdramc.yaml b/Documentation/devicetree/bindings/arm/atmel,at91rm9200-sdramc.yaml
> new file mode 100644
> index 000000000000..1516fc8e09e1
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/atmel,at91rm9200-sdramc.yaml
> @@ -0,0 +1,67 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/arm/atmel,at91rm9200-sdramc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Microchip (Atmel) SDRAM / DDR Controller (RAMC / DDRAMC / UDDRC)
> +
> +maintainers:
> + - Nicolas Ferre <nicolas.ferre@xxxxxxxxxxxxx>
> + - Claudiu Beznea <claudiu.beznea@xxxxxxxxx>
> +
> +description:
> + The SDRAM/DDR Controller (often called RAMC or DDRAMC) in various
> + Atmel/Microchip ARM9 and Cortex-A5/A7 SoCs manages external
> + SDRAM / DDR memory. It is typically exposed as a syscon node for
> + register access from other drivers (e.g. for initialization or mode
> + configuration). No interrupts or clocks are usually required in the
> + binding.
> +
> +properties:
> + compatible:
> + oneOf:
> + - items:
> + - const: atmel,at91rm9200-sdramc
> + - const: syscon
> + - items:
> + - const: microchip,sama7d65-uddrc
> + - const: microchip,sama7g5-uddrc
> + - items:
> + enum:

Whoops, sorry for not noticing this earlier, but an items list with one
entry can be reduced to that one entry. For you here that means that
"- items enum:" becomes "- enum:".

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