Re: [PATCH] riscv: add system error interrupt handler support
From: kernel test robot
Date: Thu Feb 26 2026 - 14:13:16 EST
Hi Rui,
kernel test robot noticed the following build errors:
[auto build test ERROR on linus/master]
[also build test ERROR on tip/smp/core v7.0-rc1 next-20260226]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Rui-Qi/riscv-add-system-error-interrupt-handler-support/20260226-163131
base: linus/master
patch link: https://lore.kernel.org/r/20260226082735.56108-1-qirui.001%40bytedance.com
patch subject: [PATCH] riscv: add system error interrupt handler support
config: riscv-randconfig-r064-20260226 (https://download.01.org/0day-ci/archive/20260227/202602270355.h8QSG2vl-lkp@xxxxxxxxx/config)
compiler: riscv32-linux-gcc (GCC) 8.5.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260227/202602270355.h8QSG2vl-lkp@xxxxxxxxx/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@xxxxxxxxx>
| Closes: https://lore.kernel.org/oe-kbuild-all/202602270355.h8QSG2vl-lkp@xxxxxxxxx/
All errors (new ones prefixed by >>):
In file included from arch/riscv/include/asm/errata_list.h:8,
from arch/riscv/include/asm/vdso/processor.h:8,
from include/vdso/processor.h:10,
from arch/riscv/include/asm/processor.h:13,
from arch/riscv/include/asm/cmpxchg.h:16,
from arch/riscv/include/asm/barrier.h:14,
from include/asm-generic/bitops/generic-non-atomic.h:7,
from include/linux/bitops.h:28,
from include/linux/kernel.h:23,
from arch/riscv/kernel/sys_error.c:7:
arch/riscv/kernel/sys_error.c: In function 'riscv_serror_starting_cpu':
>> arch/riscv/kernel/sys_error.c:28:22: error: 'RV_IRQ_SYS_ERROR' undeclared (first use in this function); did you mean 'IRQ_SYS_ERROR'?
csr_set(CSR_IE, BIT(RV_IRQ_SYS_ERROR));
^~~~~~~~~~~~~~~~
arch/riscv/include/asm/csr.h:588:38: note: in definition of macro 'csr_set'
unsigned long __v = (unsigned long)(val); \
^~~
arch/riscv/kernel/sys_error.c:28:18: note: in expansion of macro 'BIT'
csr_set(CSR_IE, BIT(RV_IRQ_SYS_ERROR));
^~~
arch/riscv/kernel/sys_error.c:28:22: note: each undeclared identifier is reported only once for each function it appears in
csr_set(CSR_IE, BIT(RV_IRQ_SYS_ERROR));
^~~~~~~~~~~~~~~~
arch/riscv/include/asm/csr.h:588:38: note: in definition of macro 'csr_set'
unsigned long __v = (unsigned long)(val); \
^~~
arch/riscv/kernel/sys_error.c:28:18: note: in expansion of macro 'BIT'
csr_set(CSR_IE, BIT(RV_IRQ_SYS_ERROR));
^~~
arch/riscv/kernel/sys_error.c: In function 'riscv_serror_dying_cpu':
arch/riscv/kernel/sys_error.c:35:24: error: 'RV_IRQ_SYS_ERROR' undeclared (first use in this function); did you mean 'IRQ_SYS_ERROR'?
csr_clear(CSR_IE, BIT(RV_IRQ_SYS_ERROR));
^~~~~~~~~~~~~~~~
arch/riscv/include/asm/csr.h:605:38: note: in definition of macro 'csr_clear'
unsigned long __v = (unsigned long)(val); \
^~~
arch/riscv/kernel/sys_error.c:35:20: note: in expansion of macro 'BIT'
csr_clear(CSR_IE, BIT(RV_IRQ_SYS_ERROR));
^~~
arch/riscv/kernel/sys_error.c: In function 'sys_error_init':
arch/riscv/kernel/sys_error.c:52:51: error: 'RV_IRQ_SYS_ERROR' undeclared (first use in this function); did you mean 'IRQ_SYS_ERROR'?
riscv_sys_error_irq = irq_create_mapping(domain, RV_IRQ_SYS_ERROR);
^~~~~~~~~~~~~~~~
IRQ_SYS_ERROR
vim +28 arch/riscv/kernel/sys_error.c
25
26 static int riscv_serror_starting_cpu(unsigned int cpu)
27 {
> 28 csr_set(CSR_IE, BIT(RV_IRQ_SYS_ERROR));
29 enable_percpu_irq(riscv_sys_error_irq, irq_get_trigger_type(riscv_sys_error_irq));
30 return 0;
31 }
32
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