Re: [PATCH 03/11] arm64: dts: qcom: x1e80100: Add MIPI CSI PHY nodes

[Dmitry Baryshkov]

On Thu, Feb 26, 2026 at 02:51:08PM +0000, Bryan O'Donoghue wrote:
> Add csiphy nodes for
> 
> - csiphy0
> - csiphy1
> - csiphy2
> - csiphy4
> 
> The irregular naming of the PHYs comes directly from the hardware which for
> whatever reason skipped csiphy3.
> 
> Separating the nodes from CAMSS as we have done with the sensor I2C bus aka
> the CCI interface is justified since the CSIPHYs have their own pinouts and
> voltage rails.

Subdevices can have their own voltage rails and pins. However:
- What manages the NoC access to the CSI PHY?
- Do we need to manage the NoC clock rate somehow?
- Are clocks and power domains for CSI PHYs gated separtely, or are they
  gated at the CAMSS level?
- Are the AHB / AXI buses separate or are they shared with the CAMSS?

In other words, is CCI a good example to follow or is it rather not?

> 
> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@xxxxxxxxxx>
> ---
>  arch/arm64/boot/dts/qcom/hamoa.dtsi | 115 ++++++++++++++++++++++++++++++++++++
>  1 file changed, 115 insertions(+)
> 

-- 
With best wishes
Dmitry