Re: [PATCH v3 1/2] dt-bindings: phy: qcom: Add CSI2 C-PHY/DPHY schema

[Bryan O'Donoghue]

On 27/02/2026 09:41, Krzysztof Kozlowski wrote:
> On Thu, Feb 26, 2026 at 12:34:25PM +0000, Bryan O'Donoghue wrote:
> > Add a base schema initially compatible with x1e80100 to describe MIPI CSI2
> > PHY devices.
> >
> > The hardware can support both C-PHY and D-PHY modes. The CSIPHY devices
> > have their own pinouts on the SoC as well as their own individual voltage
> > rails.
> >
> > The need to model voltage rails on a per-PHY basis leads us to define
> > CSIPHY devices as individual nodes.
> >
> > Two nice outcomes in terms of schema and DT arise from this change.
> >
> > 1. The ability to define on a per-PHY basis voltage rails.
> > 2. The ability to require those voltage.
> >
> > We have had a complete bodge upstream for this where a single set of
> > voltage rail for all CSIPHYs has been buried inside of CAMSS.
> >
> > Much like the I2C bus which is dedicated to Camera sensors - the CCI bus in
> > CAMSS parlance, the CSIPHY devices should be individually modelled.
> >
> > Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@xxxxxxxxxx>
> > ---
> >   .../bindings/phy/qcom,x1e80100-csi2-phy.yaml       | 114 +++++++++++++++++++++
> >   1 file changed, 114 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml
> > new file mode 100644
> > index 0000000000000..c937d26ccbda9
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml
> > @@ -0,0 +1,114 @@
> > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/phy/qcom,x1e80100-csi2-phy.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Qualcomm CSI2 PHY
>
> Qualcomm SoC CSI2 PHY
>
>
> > +
> > +maintainers:
> > +  - Bryan O'Donoghue <bod@xxxxxxxxxx>
> > +
> > +description:
> > +  Qualcomm MIPI CSI2 C-PHY/D-PHY combination PHY. Connects MIPI CSI2 sensors
> > +  to Qualcomm's Camera CSI Decoder. The PHY supports both C-PHY and D-PHY
> > +  modes.
>
> So just to be clear: this is not MIPI CSI, but only the CSI PHY? There
> are no ports here, which seems fine for the phy and will be in the MIPI
> CSI block?

CAMSS ports map to the CSID - CSI Decoder yes.

> > +
> > +properties:
> > +  compatible:
> > +    const: qcom,x1e80100-csi2-phy
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  "#phy-cells":
> > +    const: 1
> > +
> > +  clocks:
> > +    maxItems: 4
> > +
> > +  clock-names:
> > +    items:
> > +      - const: csiphy
>
> probably: core or iface
>
> > +      - const: csiphy_timer
>
> timer
>
> > +      - const: camnoc_axi
>
> axi or noc
>
> > +      - const: cpas_ahb
>
> bus, ahb or cpas, depending whether this is only one ahb or this is bus of
> some cpas subblock
>
> See also: https://lore.kernel.org/all/20260115-sm6150_evk-v3-2-81526dd15543@xxxxxxxxxxxxxxxx/
>
>
> > +
> > +  interrupts:
> > +    maxItems: 1
> > +
> > +  operating-points-v2:
>
> Just true. It is not an array.

LOL I asked a chatbot to review my submission and it told me to change 
this from true to a list.

€90 subscription well spent...

Thanks for review.

---
bod