Re: [PATCH v6 08/13] PCI: tegra194: Apply pinctrl settings for both PCIe RP and EP

[Vidya Sagar]

On 24/02/26 00:11, Manikanta Maddireddy wrote:
> From: Vidya Sagar <vidyas@xxxxxxxxxx>
> 
> PERST# and CLKREQ# pinctrl settings should be applied for both root port
> and endpoint mode. Move pinctrl_pm_select_default_state() function call
> from root port specific configuration function to probe().
> 
> Fixes: c57247f940e8 ("PCI: tegra: Add support for PCIe endpoint mode in Tegra194")
> Signed-off-by: Vidya Sagar <vidyas@xxxxxxxxxx>
> Signed-off-by: Manikanta Maddireddy <mmaddireddy@xxxxxxxxxx>
> ---
> Changes V5 -> V6: None
> Changes V4 -> V5: Use dev_err_probe() function
> Changes V1 -> V4: None
> 
>  drivers/pci/controller/dwc/pcie-tegra194.c | 10 ++++------
>  1 file changed, 4 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
> index ad1056d68d6d..61cbb4f230e1 100644
> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
> @@ -1601,12 +1601,6 @@ static int tegra_pcie_config_rp(struct tegra_pcie_dw *pcie)
>  		goto fail_pm_get_sync;
>  	}
>  
> -	ret = pinctrl_pm_select_default_state(dev);
> -	if (ret < 0) {
> -		dev_err(dev, "Failed to configure sideband pins: %d\n", ret);
> -		goto fail_pm_get_sync;
> -	}
> -
>  	ret = tegra_pcie_init_controller(pcie);
>  	if (ret < 0) {
>  		dev_err(dev, "Failed to initialize controller: %d\n", ret);
> @@ -2076,6 +2070,10 @@ static int tegra_pcie_dw_probe(struct platform_device *pdev)
>  	pp = &pci->pp;
>  	pp->num_vectors = MAX_MSI_IRQS;
>  
> +	ret = pinctrl_pm_select_default_state(dev);
> +	if (ret < 0)
> +		return dev_err_probe(dev, ret, "Failed to configure sideband pins: %d\n", ret);
> +
>  	ret = tegra_pcie_dw_parse_dt(pcie);
>  	if (ret < 0) {
>  		const char *level = KERN_ERR;

Reviewed-by: Vidya Sagar <vidyas@xxxxxxxxxx>