Re: [PATCH net] amd-xgbe: fix MAC_TCR_SS register width for 2.5G and 10M speeds

From: patchwork-bot+netdevbpf

Date: Sat Feb 28 2026 - 17:30:10 EST


Hello:

This patch was applied to netdev/net.git (main)
by Jakub Kicinski <kuba@xxxxxxxxxx>:

On Thu, 26 Feb 2026 22:37:53 +0530 you wrote:
> Extend the MAC_TCR_SS (Speed Select) register field width from 2 bits
> to 3 bits to properly support all speed settings.
>
> The MAC_TCR register's SS field encoding requires 3 bits to represent
> all supported speeds:
> - 0x00: 10Gbps (XGMII)
> - 0x02: 2.5Gbps (GMII) / 100Mbps
> - 0x03: 1Gbps / 10Mbps
> - 0x06: 2.5Gbps (XGMII) - P100a only
>
> [...]

Here is the summary with links:
- [net] amd-xgbe: fix MAC_TCR_SS register width for 2.5G and 10M speeds
https://git.kernel.org/netdev/net/c/9439a661c2e8

You are awesome, thank you!
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