Re: [PATCH v2 2/2] PCI: sg2042: Avoid L0s and L1 on Sophgo 2042 PCIe Root Ports

[Inochi Amaoto]

On Fri, Feb 27, 2026 at 06:24:12PM +0000, Yao Zi wrote:
> On Fri, Feb 27, 2026 at 06:19:25PM +0000, Yao Zi wrote:
> > Since commit f3ac2ff14834 ("PCI/ASPM: Enable all ClockPM and ASPM
> > states for devicetree platforms") force enable ASPM on all device tree
> > platform, the SG2042 root port breaks as it advertises L0s and L1
> > capabilities without supporting it.
> > 
> > Provide a platform-specific initialization hook to override the L0s and
> > L1 support advertised in LNKCAP register of SG2042 Root Ports, so it
> > doesn't try to enable those states.
> > 
> > Fixes: 4e27aca4881a ("riscv: sophgo: dts: add PCIe controllers for SG2042")
> > Co-authored-by: Inochi Amaoto <inochiama@xxxxxxxxx>
> 
> Oops, this should be Co-developed-by instead of Co-authored-by, sorry
> for the silly mistake...
> 
> > Signed-off-by: Inochi Amaoto <inochiama@xxxxxxxxx>
> > Signed-off-by: Yao Zi <me@xxxxxxxx>
> 
> Regards,
> Yao Zi

Thanks, and this patch is LGTM.

With the tag fixed:

Reviewed-by: Inochi Amaoto <inochiama@xxxxxxxxx>

Regards,
Inochi