Re: [PATCH v6 1/9] PCI: tegra194: Drive CLKREQ signal low explicitly

[Manikanta Maddireddy]

On 03/03/26 5:04 am, Bjorn Helgaas wrote:
> On Fri, Feb 27, 2026 at 12:35:31PM +0000, Vidya Sagar wrote:
> > On 24/02/26 00:15, Manikanta Maddireddy wrote:
> > > From: Vidya Sagar <vidyas@xxxxxxxxxx>
> > >
> > > Currently, the default setting is that CLKREQ signal of a Root Port
> > > is internally overridden to '0' to enable REFCLK to flow out to the slot.
> > > It is observed that one of the PCIe switches (case in point Broadcom PCIe
> > > Gen4 switch) is propagating the CLKREQ signal of the root port to the
> > > downstream side of the switch and expecting the endpoints to pull it low
> > > so that it (PCIe switch) can give out the REFCLK although the Switch as
> > > such doesn't support CLK-PM or ASPM-L1SS. So, as a workaround, this patch
> > > drives the CLKREQ of the Root Port itself low to avoid link up issues
> > > between PCIe switch downstream port and endpoints. This is not a wrong
> > > thing to do after all the CLKREQ is anyway being overridden to '0'
> > > internally and now it is just that the same is being propagated outside
> > > also.
>
> Inconsistent styling of "Root Port", "root port".  Spec uses
> "CLKREQ#".
>
> > > Signed-off-by: Vidya Sagar <vidyas@xxxxxxxxxx>
> > > Signed-off-by: Manikanta Maddireddy <mmaddireddy@xxxxxxxxxx>
>
> > Reviewed-by: Vidya Sagar <vidyas@xxxxxxxxxx>
>
> A Reviewed-by tag here seems a little weird since you're the source of
> the patch.  I'm not sure what that would mean.

This series is originally from "Vidya Sagar", I picked up this series 
now. I added few new patches to the series, I will add Vidya Sagar's
review tag to only these new patches.

Thanks,
Manikanta

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nvpublic