Re: [PATCH] iommu/dma: Rate-limit WARN in iommu_dma_unmap_phys()

[Breno Leitao]

hello Leon,

On Fri, Feb 13, 2026 at 01:23:55PM +0200, Leon Romanovsky wrote:
> On Wed, Feb 11, 2026 at 07:13:03AM -0800, Breno Leitao wrote:
> > When a PCI error (e.g. AER error or DPC containment) marks the PCI
> > channel as frozen or permanently failed, the IOMMU mappings for the
> > device may already be torn down. If a driver continues processing
> > completions in this state, every call to dma_unmap_page() triggers a
> > WARN_ON in iommu_dma_unmap_phys().
> > 
> > In a real-world crash scenario on an NVIDIA Grace (ARM64) platform, a
> > DPC event froze the PCI channel and the mlx5 NAPI poll continued
> > processing error CQEs, calling dma_unmap for each pending WQE. With
> > dozens of pending WQEs, the resulting WARN_ON storm monopolized the CPU
> > in softirq context for over 23 seconds, triggering a soft lockup panic.
> > 
> > Replace WARN_ON(!phys) with WARN_RATELIMIT() to cap the warning output
> > at the kernel's default rate limit (10 messages per 5 seconds), while
> > still providing visibility into the failure with the device name in the
> > message.
> > 
> > Signed-off-by: Breno Leitao <leitao@xxxxxxxxxx>
> > Fixes: 82612d66d51d ("iommu: Allow the dma-iommu api to use bounce buffers")
> > ---
> > I initially attempted to fix this in the driver itself, but that approach
> > doesn't appear to be optimal, given the mappings can go away at any
> > time, which is impossible to check at any time. Please see the discussion at:
> > 
> > https://lore.kernel.org/all/20260209-mlx5_iommu-v1-1-b17ae501aeb2@xxxxxxxxxx/
> > ---
> >  drivers/iommu/dma-iommu.c | 3 ++-
> >  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> We have similar failure in our regression and the proposal fix is below,
> can you please try if it fixes your issue too?

This is not a trivial test to run, but, the early tested showed some good
results.

I will report back if I find regressions later,

Thanks for the fix,
--breno