Re: [PATCH 5/5] clk: qcom: dispcc[01]-sa8775p: Fix DSI byte clock rate setting

[Dmitry Baryshkov]

On Wed, Mar 04, 2026 at 02:48:31PM +0100, Konrad Dybcio wrote:
> From: Konrad Dybcio <konrad.dybcio@xxxxxxxxxxxxxxxx>
> 
> The clock tree for byte_clk_src is as follows:
> 
>    ┌──────byte0_clk_src─────┐
>    │                        │
> byte0_clk            byte0_div_clk_src
>                             │
>                      byte0_intf_clk
> 
> If both of its direct children have CLK_SET_RATE_PARENT with different
> requests, byte0_clk_src (and its parent) will be reconfigured. In this
> case, byte0_intf should strictly follow the rate of byte0_clk (with
> some adjustments based on PHY mode).
> 
> Remove CLK_SET_RATE_PARENT from byte0_div_clk_src to avoid this issue.
> 
> Fixes: e700bfd2f976 ("clk: qcom: Add support for Display clock Controllers on SA8775P")
> Signed-off-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxxxxxxxx>
> ---
>  drivers/clk/qcom/dispcc0-sa8775p.c | 2 --
>  drivers/clk/qcom/dispcc1-sa8775p.c | 2 --
>  2 files changed, 4 deletions(-)

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxxxxxxxx>


-- 
With best wishes
Dmitry