Re: [PATCH v2] mmc: sdhci-pci-gli: fix GL9750 DMA write corruption

[Ulf Hansson]

On Mon, 2 Mar 2026 at 22:08, Matthew Schwartz
<matthew.schwartz@xxxxxxxxx> wrote:
>
> The GL9750 SD host controller has intermittent data corruption during
> DMA write operations. The GM_BURST register's R_OSRC_Lmt field
> (bits 17:16), which limits outstanding DMA read requests from system
> memory, is not being cleared during initialization. The Windows driver
> sets R_OSRC_Lmt to zero, limiting requests to the smallest unit.
>
> Clear R_OSRC_Lmt to match the Windows driver behavior. This eliminates
> write corruption verified with f3write/f3read tests while maintaining
> DMA performance.
>
> Cc: stable@xxxxxxxxxxxxxxx
> Fixes: e51df6ce668a ("mmc: host: sdhci-pci: Add Genesys Logic GL975x support")
> Closes: https://lore.kernel.org/linux-mmc/33d12807-5c72-41ce-8679-57aa11831fad@xxxxxxxxx/
> Acked-by: Adrian Hunter <adrian.hunter@xxxxxxxxx>
> Signed-off-by: Matthew Schwartz <matthew.schwartz@xxxxxxxxx>

Applied for fixes, thanks!

Kind regards
Uffe


> ---
> Changes in v2:
> - Move GM_BURST register defines
> - Clear R_OSRC_Lmt in gli_set_9750 instead of gl9750_hw_setting to survive resets
> - Link to v1: https://lore.kernel.org/linux-mmc/20260227075909.3860183-1-matthew.schwartz@xxxxxxxxx/
>
> Changes in v1:
> - Use the proper name for the register field
> - Link to RFC: https://lore.kernel.org/linux-mmc/20260117234800.931664-1-matthew.schwartz@xxxxxxxxx/
> ---
>  drivers/mmc/host/sdhci-pci-gli.c | 9 +++++++++
>  1 file changed, 9 insertions(+)
>
> diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhci-pci-gli.c
> index b0f91cc9e40e4..6e4084407662a 100644
> --- a/drivers/mmc/host/sdhci-pci-gli.c
> +++ b/drivers/mmc/host/sdhci-pci-gli.c
> @@ -68,6 +68,9 @@
>  #define   GLI_9750_MISC_TX1_DLY_VALUE    0x5
>  #define   SDHCI_GLI_9750_MISC_SSC_OFF    BIT(26)
>
> +#define SDHCI_GLI_9750_GM_BURST_SIZE             0x510
> +#define   SDHCI_GLI_9750_GM_BURST_SIZE_R_OSRC_LMT  GENMASK(17, 16)
> +
>  #define SDHCI_GLI_9750_TUNING_CONTROL            0x540
>  #define   SDHCI_GLI_9750_TUNING_CONTROL_EN          BIT(4)
>  #define   GLI_9750_TUNING_CONTROL_EN_ON             0x1
> @@ -345,10 +348,16 @@ static void gli_set_9750(struct sdhci_host *host)
>         u32 misc_value;
>         u32 parameter_value;
>         u32 control_value;
> +       u32 burst_value;
>         u16 ctrl2;
>
>         gl9750_wt_on(host);
>
> +       /* clear R_OSRC_Lmt to avoid DMA write corruption */
> +       burst_value = sdhci_readl(host, SDHCI_GLI_9750_GM_BURST_SIZE);
> +       burst_value &= ~SDHCI_GLI_9750_GM_BURST_SIZE_R_OSRC_LMT;
> +       sdhci_writel(host, burst_value, SDHCI_GLI_9750_GM_BURST_SIZE);
> +
>         driving_value = sdhci_readl(host, SDHCI_GLI_9750_DRIVING);
>         pll_value = sdhci_readl(host, SDHCI_GLI_9750_PLL);
>         sw_ctrl_value = sdhci_readl(host, SDHCI_GLI_9750_SW_CTRL);
> --
> 2.53.0
>