Re: [PATCH] x86/cpu/centaur: Disable X86_FEATURE_FSGSBASE on Zhaoxin C4600

[Dave Hansen]

On 3/5/26 01:03, Tony W Wang-oc wrote:
> --- a/arch/x86/kernel/cpu/zhaoxin.c
> +++ b/arch/x86/kernel/cpu/zhaoxin.c
> @@ -89,6 +89,11 @@ static void init_zhaoxin(struct cpuinfo_x86 *c)
>         set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
>  #endif
> 
> +       if (c->x86 == 6 && c->x86_model == 25 && c->x86_stepping <= 3) {
> +               pr_warn_once("CPU has broken FSGSBASE support; clear
> FSGSBASE feature\n");
> +               setup_clear_cpu_cap(X86_FEATURE_FSGSBASE);
> +       }
> +

Folks, we have vendor-generic infrastructure to handle these today. You
don't need to hack copied and pasted code across vendor-specific files.
You just need some "VFM" defines for the models:

#define Z_MODEL_HERE	VFM_MAKE(X86_VENDOR_ZHAOXIN, 6, 26)
#define C_MODEL_HERE	VFM_MAKE(X86_VENDOR_ZHAOXIN, ...)

a table:

static const struct x86_cpu_id bum_fsgsbase[] __initconst = {
	X86_MATCH_VFM_STEPS(Z_MODEL_HERE, X86_STEP_MIN, 0x3, 1),
	X86_MATCH_VFM_STEPS(C_MODEL_HERE, ..., 1),
};

and this code:

	if (x86_match_cpu(bum_fsgsbase))
		setup_clear_cpu_cap(X86_FEATURE_FSGSBASE);

That code happens _once_. You can even call it from vendor-independent code.

If you get fixed microcode that can also be extended to store a fixed
microcode version (although we're moving away from doing this on Intel).

Just please give the models some semi-sane model name.