Re: [PATCH v3 1/5] dt-bindings: PCI: Convert nvidia,tegra-pcie to DT schema

[Rob Herring]

On Tue, Feb 24, 2026 at 05:48:57PM +0530, Anand Moon wrote:
> Convert the existing text-based DT bindings documentation for the
> NVIDIA Tegra PCIe host controller to a DT schema format.

I just reviewed the same thing from Thierry... This one looks a bit 
better for overall structure (fewer if/then schemas), but I think misses 
some things like deprecated supplies. Please resolve the differences 
between the 2 and coordinate who is going to send the next version.

> 
> Also update the MAINTAINERS file to reflect this change.
> 
> Cc: Jon Hunter <jonathanh@xxxxxxxxxx>
> Signed-off-by: Anand Moon <linux.amoon@xxxxxxxxx>
> ---
> v3: Tried to address the issues Krzysztof pointed out.
>    Added missing regulator binding as suggeested by Jon.
> v2: Tried to address the isssue Rob pointed
> [1] https://lkml.org/lkml/2025/9/26/704
> improve the $suject and commit message
> drop few examples only nvidia,tegra20-pcie and nvidia,tegra210-pcie
> 
> $ make dt_binding_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/pci/nvidia,tegra-pcie.yaml
> ---
>  .../bindings/pci/nvidia,tegra-pcie.yaml       | 528 ++++++++++++++
>  .../bindings/pci/nvidia,tegra20-pcie.txt      | 670 ------------------
>  MAINTAINERS                                   |   2 +-
>  3 files changed, 529 insertions(+), 671 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/pci/nvidia,tegra-pcie.yaml
>  delete mode 100644 Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
> 
> diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra-pcie.yaml b/Documentation/devicetree/bindings/pci/nvidia,tegra-pcie.yaml
> new file mode 100644
> index 000000000000..0675bec205e8
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/nvidia,tegra-pcie.yaml
> @@ -0,0 +1,528 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pci/nvidia,tegra-pcie.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: NVIDIA Tegra PCIe Controller
> +
> +maintainers:
> +  - Jon Hunter <jonathanh@xxxxxxxxxx>
> +  - Thierry Reding <treding@xxxxxxxxxx>
> +
> +description:
> +  PCIe controller found on NVIDIA Tegra SoCs which supports multiple
> +  root ports and platform-specific clock, reset, and power supply
> +  configurations.
> +
> +properties:
> +  compatible:
> +    enum:
> +      - nvidia,tegra20-pcie
> +      - nvidia,tegra30-pcie
> +      - nvidia,tegra124-pcie
> +      - nvidia,tegra210-pcie
> +      - nvidia,tegra186-pcie
> +
> +  reg:
> +    items:
> +      - description: PADS registers
> +      - description: AFI registers
> +      - description: Configuration space region
> +
> +  reg-names:
> +    items:
> +      - const: pads
> +      - const: afi
> +      - const: cs
> +
> +  interrupts:
> +    items:
> +      - description: Controller interrupt
> +      - description: MSI interrupt
> +
> +  interrupt-names:
> +    items:
> +      - const: intr
> +      - const: msi
> +
> +  clocks:
> +    minItems: 3
> +    items:
> +      - description: PCIe clock
> +      - description: AFI clock
> +      - description: PLL_E clock
> +      - description: Optional CML clock
> +
> +  clock-names:
> +    description: Names of clocks used by the PCIe controller
> +    minItems: 3
> +    items:
> +      - const: pex
> +      - const: afi
> +      - const: pll_e
> +      - const: cml
> +
> +  resets:
> +    items:
> +      - description: PCIe reset
> +      - description: AFI reset
> +      - description: PCIe-X reset
> +
> +  reset-names:
> +    items:
> +      - const: pex
> +      - const: afi
> +      - const: pcie_x
> +
> +  power-domains:
> +    maxItems: 1
> +
> +  interconnects:
> +    minItems: 1
> +    maxItems: 2
> +
> +  interconnect-names:
> +    items:
> +      - const: dma-mem
> +      - const: write
> +
> +  pinctrl-names:
> +    items:
> +      - const: default
> +      - const: idle
> +
> +  pinctrl-0: true
> +  pinctrl-1: true
> +
> +  operating-points-v2:
> +    description:
> +      Defines operating points with required frequency and voltage values,
> +      and the opp-supported-hw property.
> +
> +  iommus:
> +    maxItems: 1
> +
> +  avdd-pex-supply:
> +    description: Power supply for analog PCIe logic. Must supply 1.05 V.
> +
> +  vdd-pex-supply:
> +    description: Power supply for digital PCIe I/O. Must supply 1.05 V.
> +
> +  avdd-pex-pll-supply:
> +    description: Power supply for dedicated (internal) PCIe PLL. Must supply 1.05 V.
> +
> +  avdd-plle-supply:
> +    description: Power supply for PLLE, which is shared with SATA. Must supply 1.05 V.
> +
> +  vddio-pex-clk-supply:
> +    description: Power supply for PCIe clock. Must supply 3.3 V.
> +
> +  vddio-pex-ctl-supply:
> +    description: Power supply for PCIe control I/O partition. Must supply 1.8 V.
> +
> +  hvdd-pex-supply:
> +    description: High-voltage supply for PCIe I/O and PCIe output clocks. Must supply 3.3 V.
> +
> +  avdd-pexa-supply:
> +    description: Power supply for analog PCIe logic. Must supply 1.05 V.
> +
> +  vdd-pexa-supply:
> +    description: Power supply for digital PCIe I/O. Must supply 1.05 V.
> +
> +  avdd-pexb-supply:
> +    description: Power supply for analog PCIe logic. Must supply 1.05 V.
> +
> +  vdd-pexb-supply:
> +    description: Power supply for digital PCIe I/O. Must supply 1.05 V.
> +
> +  avddio-pex-supply:
> +    description: Power supply for analog PCIe logic. Must supply 1.05 V.
> +
> +  dvddio-pex-supply:
> +    description: Power supply for digital PCIe I/O. Must supply 1.05 V.
> +
> +  hvddio-pex-supply:
> +    description: High-voltage supply for PCIe I/O and PCIe output clocks. Must supply 1.8 V.
> +
> +  dvdd-pex-supply:
> +    description: Power supply for digital PCIe I/O. Must supply 1.05 V.
> +
> +  hvdd-pex-pll-supply:
> +    description: High-voltage supply for PLLE (shared with USB3). Must supply 1.8 V.
> +
> +  vddio-pexctl-aud-supply:
> +    description: Power supply for PCIe side band signals. Must supply 1.8 V.
> +
> +patternProperties:
> +  "^pci@[0-9a-f]+(,[0-9a-f]+)?$":
> +    type: object
> +    allOf:

Don't need allOf.

> +      - $ref: /schemas/pci/pci-pci-bridge.yaml#
> +    properties:
> +      reg:
> +        maxItems: 1
> +
> +      nvidia,num-lanes:
> +        description: Number of lanes used by this PCIe port
> +        $ref: /schemas/types.yaml#/definitions/uint32
> +        enum: [1, 2, 4]
> +
> +      phys:
> +        description: Phandles to PCIe PHYs
> +        items:
> +          maxItems: 1

How many cells a phy entry has depends on the provider which is outside 
the scope of this binding.

> +        minItems: 1
> +        maxItems: 4