[PATCH 8/8] iommu/vt-d: Use intel_pasid_write() for nested setup

From: Lu Baolu

Date: Mon Mar 09 2026 - 02:10:46 EST


Refactor intel_pasid_setup_nested() to utilize the intel_pasid_write()
helper. Move the implementation to the entry_sync infrastructure, where
the nested PASID entry is constructed in a local buffer and committed
via the centralized intel_pasid_write() wrapper.

Signed-off-by: Lu Baolu <baolu.lu@xxxxxxxxxxxxxxx>
---
drivers/iommu/intel/nested.c | 13 +------------
drivers/iommu/intel/pasid.c | 27 +++++----------------------
2 files changed, 6 insertions(+), 34 deletions(-)

diff --git a/drivers/iommu/intel/nested.c b/drivers/iommu/intel/nested.c
index 2b979bec56ce..1cebc1232f70 100644
--- a/drivers/iommu/intel/nested.c
+++ b/drivers/iommu/intel/nested.c
@@ -131,17 +131,6 @@ static int intel_nested_cache_invalidate_user(struct iommu_domain *domain,
return ret;
}

-static int domain_setup_nested(struct intel_iommu *iommu,
- struct dmar_domain *domain,
- struct device *dev, ioasid_t pasid,
- struct iommu_domain *old)
-{
- if (old)
- intel_pasid_tear_down_entry(iommu, dev, pasid, false);
-
- return intel_pasid_setup_nested(iommu, dev, pasid, domain);
-}
-
static int intel_nested_set_dev_pasid(struct iommu_domain *domain,
struct device *dev, ioasid_t pasid,
struct iommu_domain *old)
@@ -170,7 +159,7 @@ static int intel_nested_set_dev_pasid(struct iommu_domain *domain,
if (ret)
goto out_remove_dev_pasid;

- ret = domain_setup_nested(iommu, dmar_domain, dev, pasid, old);
+ ret = intel_pasid_setup_nested(iommu, dev, pasid, dmar_domain);
if (ret)
goto out_unwind_iopf;

diff --git a/drivers/iommu/intel/pasid.c b/drivers/iommu/intel/pasid.c
index cb55ff422d7d..5e0548dd8388 100644
--- a/drivers/iommu/intel/pasid.c
+++ b/drivers/iommu/intel/pasid.c
@@ -754,12 +754,8 @@ static void pasid_pte_config_nestd(struct intel_iommu *iommu,
{
struct pt_iommu_vtdss_hw_info pt_info;

- lockdep_assert_held(&iommu->lock);
-
pt_iommu_vtdss_hw_info(&s2_domain->sspt, &pt_info);

- pasid_clear_entry(pte);
-
if (s1_cfg->addr_width == ADDR_WIDTH_5LEVEL)
pasid_set_flpm(pte, 1);

@@ -806,7 +802,9 @@ int intel_pasid_setup_nested(struct intel_iommu *iommu, struct device *dev,
struct iommu_hwpt_vtd_s1 *s1_cfg = &domain->s1_cfg;
struct dmar_domain *s2_domain = domain->s2_domain;
u16 did = domain_id_iommu(domain, iommu);
- struct pasid_entry *pte;
+ struct pasid_entry new_pte = {0};
+
+ iommu_group_mutex_assert(dev);

/* Address width should match the address width supported by hardware */
switch (s1_cfg->addr_width) {
@@ -837,23 +835,8 @@ int intel_pasid_setup_nested(struct intel_iommu *iommu, struct device *dev,
return -EINVAL;
}

- spin_lock(&iommu->lock);
- pte = intel_pasid_get_entry(dev, pasid);
- if (!pte) {
- spin_unlock(&iommu->lock);
- return -ENODEV;
- }
- if (pasid_pte_is_present(pte)) {
- spin_unlock(&iommu->lock);
- return -EBUSY;
- }
-
- pasid_pte_config_nestd(iommu, pte, s1_cfg, s2_domain, did);
- spin_unlock(&iommu->lock);
-
- pasid_flush_caches(iommu, pte, pasid, did);
-
- return 0;
+ pasid_pte_config_nestd(iommu, &new_pte, s1_cfg, s2_domain, did);
+ return intel_pasid_write(iommu, dev, pasid, (u128 *)&new_pte);
}

/*
--
2.43.0