Re: [patch 04/14] x86/irq: Make irqstats array based

[Thomas Gleixner]

On Mon, Mar 09 2026 at 18:12, Dmitry Ilvokhin wrote:
> On Wed, Mar 04, 2026 at 07:55:45PM +0100, Thomas Gleixner wrote:
>> +	ISS(ICR_READ_RETRY,		"RTR", " APIC ICR read retries\n"),
>> +	ISS(X86_PLATFORM_IPI,		"PLT", " Platform interrupts\n"),
>
> The old code only showed "PLT" when x86_platform_ipi_callback was set,
> but with ISS() this is now unconditional.
>
> Is this intentional?

Yes because I didn't want to add yet another conditional of dubious value.

> [...]
>
>> -	seq_printf(p, "%*s: %10u\n", prec, "ERR", atomic_read(&irq_err_count));
>> -#if defined(CONFIG_X86_IO_APIC)
>> -	seq_printf(p, "%*s: %10u\n", prec, "MIS", atomic_read(&irq_mis_count));
>> +	ITS(HYPERV_REENLIGHTMENT,	"HRE", " Hyper-V reenlightment interrupts\n"),
>
> HYPERV_REENLIGHTMENT doesn't match the enum (HYPERV_REENLIGHTENMENT).
> This should break the build with CONFIG_HYPERV=y. There is also a same
> typo in text description.

Michael pointed that out already. Fixed locally.

>> +	seq_printf(p, "ERR: %10u\n", (unsigned int) atomic_read(&irq_err_count));
>> +	if (IS_ENABLED(CONFIG_X86_IO_APIC))
>> +		seq_printf(p, "MIS: %10u\n", (unsigned int) atomic_read(&irq_mis_count));
>
> This drops the prec-based alignment for ERR and MIS.

Indeed.