Re: [PATCH v2 1/1] x86/mce/amd: Fix VM crash during deferred error handling

[Borislav Petkov]

On Wed, Feb 18, 2026 at 04:30:25PM +0000, “William Roche wrote:
> From: William Roche <william.roche@xxxxxxxxxx>
> 
> A non Scalable MCA system may prevent access to SMCA specific registers

"may prevent"?

Please explain in the commit message the whole scenario how you're triggering
this in detail.

> like MCA_DESTAT. This is the case of QEMU/KVM VMs, where the kernel
> has to check for the SMCA feature before accessing MCA_DESTAT.
> 
> Fixes: 7cb735d7c0cb ("x86/mce: Unify AMD DFR handler with MCA Polling")
> Signed-off-by: William Roche <william.roche@xxxxxxxxxx>
> Reviewed-by: Yazen Ghannam <yazen.ghannam@xxxxxxx>
> Cc: stable@xxxxxxxxxxxxxxx

AFAIR, you're injecting errors. This is not really a critical fix that
warrants this going to stable.

> ---
>  arch/x86/kernel/cpu/mce/amd.c | 17 +++++++++++------
>  1 file changed, 11 insertions(+), 6 deletions(-)
> 
> diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c
> index 3f1dda355307..7b9932f13bca 100644
> --- a/arch/x86/kernel/cpu/mce/amd.c
> +++ b/arch/x86/kernel/cpu/mce/amd.c
> @@ -875,13 +875,18 @@ void amd_clear_bank(struct mce *m)
>  {
>  	amd_reset_thr_limit(m->bank);
>  
> -	/* Clear MCA_DESTAT for all deferred errors even those logged in MCA_STATUS. */
> -	if (m->status & MCI_STATUS_DEFERRED)
> -		mce_wrmsrq(MSR_AMD64_SMCA_MCx_DESTAT(m->bank), 0);
> +	if (mce_flags.smca) {

All this code should not run in a VM. So why does it?

What is the use case we're supposed to support here?

-- 
Regards/Gruss,
    Boris.

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