Re: [PATCH v7 1/9] PCI: tegra194: Drive CLKREQ# signal low explicitly

[Manivannan Sadhasivam]

On Sun, Mar 15, 2026 at 10:46:08PM +0530, Manikanta Maddireddy wrote:
> 
> 
> On 05/03/26 4:28 pm, Manivannan Sadhasivam wrote:
> > On Tue, Mar 03, 2026 at 12:27:50PM +0530, Manikanta Maddireddy wrote:
> > > From: Vidya Sagar <vidyas@xxxxxxxxxx>
> > > 
> > > Currently, the default setting is that CLKREQ# signal of a Root Port
> > > is internally overridden to '0' to enable REFCLK to flow out to the slot.
> > > It is observed that one of the PCIe switches (case in point Broadcom PCIe
> > > Gen4 switch) is propagating the CLKREQ# signal of the Root Port to the
> > > downstream side of the switch and expecting the Endpoint devices to pull
> > > it low so that it (PCIe switch) can give out the REFCLK although the Switch
> > > as such doesn't support CLK-PM or ASPM-L1SS. So, as a workaround, this
> > > patch drives the CLKREQ# of the Root Port itself low to avoid link up
> > > issues between PCIe switch downstream port and Endpoint devices. This is
> > 
> > Is the CLKREQ# signal shared with the switch and the endpoint devices
> > connected to its downstream port also?
> > 
> Yes, this is the observation.
> 
> > > not a wrong thing to do after all the CLKREQ# is anyway being overridden
> > > to '0' internally and now it is just that the same is being propagated
> > > outside also.
> > > 
> > 
> > What do you mean by 'propagating outside'?
> > 
> > And what is the difference between APPL_PINMUX_CLKREQ_OVERRIDE and
> > APPL_PINMUX_CLKREQ_DEFAULT_VALUE?
> > 
> > - Mani
> APPL_PINMUX_CLKREQ_OVERRIDE: This overrides CLKREQ# input PAD to PCIe
> controller.
> APPL_PINMUX_CLKREQ_OVERRIDE: This overrides CLKREQ# output PAD to low.
> Propagating outside means driving CLKREQ# pin as low.
> 

>From the commit message, it looks like APPL_PINMUX_CLKREQ_OVERRIDE itself
drivers the CLKREQ# signal to low (0), so it is not clear to me what this new
APPL_PINMUX_CLKREQ_DEFAULT_VALUE setting does.

- Mani

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