Re: [PATCH v2 2/3] clk: mediatek: mt8192: use MUX_CLR_SET

[Chen-Yu Tsai]

On Thu, Mar 26, 2026 at 1:10 PM Daniel Golle <daniel@xxxxxxxxxxxxxx> wrote:
>
> The mfg_pll_sel mux has neither a clock gate nor an update register,
> and upd_ofs is stored as u32, so the -1 truncates to 0xFFFFFFFF.
>
> While upd_shift being -1 (as s8) prevents the update path from
> executing at runtime, the bogus upd_ofs value is still stored in the
> struct.
>
> Use MUX_CLR_SET to avoid passing sentinel values to wrongly-typed
> fields.
>
> Fixes: 710573dee31b4 ("clk: mediatek: Add MT8192 basic clocks support")
> Signed-off-by: Daniel Golle <daniel@xxxxxxxxxxxxxx>

Reviewed-by: Chen-Yu Tsai <wenst@xxxxxxxxxxxx>