[PATCH 0/5] Support additional AMD EILVT registers

[Naveen N Rao (AMD)]

Future AMD processors will be increasing the number of APIC EILVT 
registers (*). This series adds support for the same along with some 
related cleanups.

(*) https://docs.amd.com/v/u/en-US/69205_1.00_AMD64_IBS_PUB)


- Naveen


Naveen N Rao (AMD) (5):
  x86/apic: Drop AMD Extended Interrupt LVT macros
  x86/apic: Drop unused AMD EILVT macros
  perf/amd/ibs: Limit the max EILVT register count for AMD family 0x10
  x86/apic: Introduce a variable to track the number of EILVT registers
  x86/apic: Drop APIC_EILVT_NR_MAX and switch to using apic_eilvt_count

 arch/x86/include/asm/apic.h    |  2 ++
 arch/x86/include/asm/apicdef.h |  9 +--------
 arch/x86/events/amd/ibs.c      | 10 +++++-----
 arch/x86/kernel/apic/apic.c    | 33 +++++++++++++++++++++++++--------
 arch/x86/kernel/cpu/mce/amd.c  |  6 +++---
 5 files changed, 36 insertions(+), 24 deletions(-)


base-commit: cf112712c193e837225d740ec3e139774f2496f2
-- 
2.53.0