[PATCH v3] Add remoteproc PAS loader for SoCCP on Glymur DT
From: Ananthu C V
Date: Fri Apr 03 2026 - 07:40:40 EST
From: Sibi Sankar <sibi.sankar@xxxxxxxxxxxxxxxx>
Signed-off-by: Sibi Sankar <sibi.sankar@xxxxxxxxxxxxxxxx>
Co-developed-by: Ananthu C V <ananthu.cv@xxxxxxxxxxxxxxxx>
Signed-off-by: Ananthu C V <ananthu.cv@xxxxxxxxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/glymur-crd.dtsi | 7 +++++
arch/arm64/boot/dts/qcom/glymur.dtsi | 47 ++++++++++++++++++++++++++++++++
2 files changed, 54 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi
index 2852d257ac8c..3fdf8dbbde02 100644
--- a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi
+++ b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi
@@ -560,6 +560,13 @@ &pon_resin {
status = "okay";
};
+&remoteproc_soccp {
+ firmware-name = "qcom/glymur/soccp.mbn",
+ "qcom/glymur/soccp_dtb.mbn";
+
+ status = "okay";
+};
+
&tlmm {
gpio-reserved-ranges = <4 4>, /* EC TZ Secure I3C */
<10 2>, /* OOB UART */
diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
index f23cf81ddb77..f7f3374a5e08 100644
--- a/arch/arm64/boot/dts/qcom/glymur.dtsi
+++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
@@ -2264,6 +2264,53 @@ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
};
};
+ remoteproc_soccp: remoteproc-soccp@d00000 {
+ compatible = "qcom,glymur-soccp-pas", "qcom,kaanapali-soccp-pas";
+ reg = <0x0 0x00d00000 0x0 0x200000>;
+
+ interrupts-extended = <&intc GIC_SPI 167 IRQ_TYPE_EDGE_RISING>,
+ <&soccp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&soccp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&soccp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&soccp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
+ <&soccp_smp2p_in 9 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog",
+ "fatal",
+ "ready",
+ "handover",
+ "stop-ack",
+ "pong";
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "xo";
+
+ power-domains = <&rpmhpd RPMHPD_CX>,
+ <&rpmhpd RPMHPD_MX>;
+ power-domain-names = "cx",
+ "mx";
+
+ memory-region = <&soccp_mem>,
+ <&soccpdtb_mem>;
+
+ qcom,smem-states = <&soccp_smp2p_out 0>,
+ <&soccp_smp2p_out 8>;
+ qcom,smem-state-names = "stop",
+ "ping";
+
+ status = "disabled";
+
+ glink-edge {
+ interrupts-extended = <&ipcc IPCC_MPROC_SOCCP
+ IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc IPCC_MPROC_SOCCP
+ IPCC_MPROC_SIGNAL_GLINK_QMP>;
+ qcom,remote-pid = <19>;
+ label = "soccp";
+
+ };
+ };
+
usb_hs_phy: phy@fa0000 {
compatible = "qcom,glymur-m31-eusb2-phy",
"qcom,sm8750-m31-eusb2-phy";
---
base-commit: bd0f139e5fc11182777b81cefc3893ea508544ec
change-id: 20260403-glymur-soccp-2ca25f3b30e2
prerequisite-message-id: <20260326-knp-soccp-dt-v1-0-a60c2ae36e9b@xxxxxxxxxxxxxxxx>
prerequisite-patch-id: fa390011ee531589a7ad14250d158f497622efbd
prerequisite-patch-id: 93e7fca58a5c06edefa624ec2b006dd80f4749a8
prerequisite-patch-id: 99a3b6a7fcd061267b40097ad25f652ebe0a4c7b
Best regards,
--
Ananthu C V <ananthu.cv@xxxxxxxxxxxxxxxx>