[PATCH 06/12] arm64: dts: qcom: qcs6490-radxa-dragon-q6a: Drop QSPI node and reserve its pins

[Xilin Wu]

The latest official boot firmware configures TrustZone to restrict
direct access to the QSPI controller. Any attempt to access it from
the non-secure world causes an immediate board reset.

Remove the QSPI flash node and its associated pinctrl states, mark
GPIOs 12-17 as reserved, and protect the QSPI clocks in the GCC
node to prevent the kernel from touching this hardware.

Signed-off-by: Xilin Wu <sophon@xxxxxxxxx>
---
 .../boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts     | 60 +++-------------------
 1 file changed, 7 insertions(+), 53 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
index 91f1b4f57915..8d6bb4b0724b 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
+++ b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
@@ -513,6 +513,9 @@ &gcc {
 			   <GCC_MSS_Q6SS_BOOT_CLK_SRC>,
 			   <GCC_MSS_Q6_MEMNOC_AXI_CLK>,
 			   <GCC_MSS_SNOC_AXI_CLK>,
+			   <GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
+			   <GCC_QSPI_CORE_CLK>,
+			   <GCC_QSPI_CORE_CLK_SRC>,
 			   <GCC_SEC_CTRL_CLK_SRC>,
 			   <GCC_WPSS_AHB_BDG_MST_CLK>,
 			   <GCC_WPSS_AHB_CLK>,
@@ -745,28 +748,6 @@ &pon_pwrkey {
 	status = "okay";
 };
 
-&qspi {
-	/* It's not possible to use QSPI with iommu */
-	/* due to an error in qcom_smmu_write_s2cr */
-	/delete-property/ iommus;
-
-	pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data0>,
-				<&qspi_data1>, <&qspi_data23>;
-	pinctrl-1 = <&qspi_sleep>;
-	pinctrl-names = "default", "sleep";
-
-	status = "okay";
-
-	spi_flash: flash@0 {
-		compatible = "winbond,w25q256", "jedec,spi-nor";
-		reg = <0>;
-
-		spi-max-frequency = <104000000>;
-		spi-tx-bus-width = <4>;
-		spi-rx-bus-width = <4>;
-	};
-};
-
 &qupv3_id_0 {
 	firmware-name = "qcom/qcm6490/qupv3fw.elf";
 	status = "okay";
@@ -906,6 +887,10 @@ wcd_tx: codec@0,3 {
 };
 
 &tlmm {
+	/*
+	 * 12-17: reserved for QSPI flash
+	 */
+	gpio-reserved-ranges = <12 6>;
 	gpio-line-names =
 		/* GPIO_0 ~ GPIO_3 */
 		"PIN_13", "PIN_15", "", "",
@@ -1024,12 +1009,6 @@ pcie1_wake_n: pcie1-wake-n-state {
 		bias-pull-up;
 	};
 
-	qspi_sleep: qspi-sleep-state {
-		pins = "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17";
-		function = "gpio";
-		output-disable;
-	};
-
 	sd_cd: sd-cd-state {
 		pins = "gpio91";
 		function = "gpio";
@@ -1210,31 +1189,6 @@ &pcie1_clkreq_n {
 	drive-strength = <2>;
 };
 
-&qspi_clk {
-	bias-disable;
-	drive-strength = <16>;
-};
-
-&qspi_cs0 {
-	bias-disable;
-	drive-strength = <8>;
-};
-
-&qspi_data0 {
-	bias-disable;
-	drive-strength = <8>;
-};
-
-&qspi_data1 {
-	bias-disable;
-	drive-strength = <8>;
-};
-
-&qspi_data23 {
-	bias-disable;
-	drive-strength = <8>;
-};
-
 &sdc1_clk {
 	bias-disable;
 	drive-strength = <16>;

-- 
2.53.0