Re: [Intel-wired-lan] [PATCH net] ice: fix missing SMA pin initialization in DPLL subsystem

[Petr Oros]

On 4/1/26 18:29, Rinitha, SX wrote:
> > -----Original Message-----
> > From: Intel-wired-lan <intel-wired-lan-bounces@xxxxxxxxxx> On Behalf Of Petr Oros
> > Sent: 13 February 2026 19:47
> > To: netdev@xxxxxxxxxxxxxxx
> > Cc: Vecera, Ivan <ivecera@xxxxxxxxxx>; Kitszel, Przemyslaw <przemyslaw.kitszel@xxxxxxxxx>; Eric Dumazet <edumazet@xxxxxxxxxx>; Kubalewski, Arkadiusz <arkadiusz.kubalewski@xxxxxxxxx>; Andrew Lunn <andrew+netdev@xxxxxxx>; Nguyen, Anthony L <anthony.l.nguyen@xxxxxxxxx>; Simon Horman <horms@xxxxxxxxxx>; intel-wired-lan@xxxxxxxxxxxxxxxx; Jakub Kicinski <kuba@xxxxxxxxxx>; Paolo Abeni <pabeni@xxxxxxxxxx>; David S. Miller <davem@xxxxxxxxxxxxx>; linux-kernel@xxxxxxxxxxxxxxx
> > Subject: [Intel-wired-lan] [PATCH net] ice: fix missing SMA pin initialization in DPLL subsystem
> >
> > The DPLL SMA/U.FL pin redesign introduced ice_dpll_sw_pin_frequency_get() which gates frequency reporting on the pin's active flag. This flag is determined by ice_dpll_sw_pins_update() from the PCA9575 GPIO expander state. Before the redesign, SMA pins were exposed as direct HW input/output pins and ice_dpll_frequency_get() returned the CGU frequency unconditionally — the PCA9575 state was never consulted.
> >
> > The PCA9575 powers on with all outputs high, setting ICE_SMA1_DIR_EN, ICE_SMA1_TX_EN, ICE_SMA2_DIR_EN and ICE_SMA2_TX_EN. Nothing in the driver writes the register during initialization, so
> > ice_dpll_sw_pins_update() sees all pins as inactive and
> > ice_dpll_sw_pin_frequency_get() permanently returns 0 Hz for every SW pin.
> >
> > Fix this by writing a default SMA configuration in
> > ice_dpll_init_info_sw_pins(): clear all SMA bits, then set SMA1 and
> > SMA2 as active inputs (DIR_EN=0) with U.FL1 output and U.FL2 input disabled. Each SMA/U.FL pair shares a physical signal path so only one pin per pair can be active at a time. U.FL pins still report frequency 0 after this fix: U.FL1 (output-only) is disabled by ICE_SMA1_TX_EN which keeps the TX output buffer off, and U.FL2
> > (input-only) is disabled by ICE_SMA2_UFL2_RX_DIS. They can be activated by changing the corresponding SMA pin direction via dpll netlink.
> >
> > Fixes: 2dd5d03c77e2 ("ice: redesign dpll sma/u.fl pins control")
> > Signed-off-by: Petr Oros <poros@xxxxxxxxxx>
> > ---
> > drivers/net/ethernet/intel/ice/ice_dpll.c | 17 +++++++++++++++++
> > 1 file changed, 17 insertions(+)
> When SMA1 is changed from output to input , U.FL1 (input) is expected to get connected but is still disconnected
> Similary, when SMA2 is changed from input to output , U.FL2 (output) is still disconnected

Hi Rinitha,

Thanks for testing this.
The initialization patch itself is correct. After boot, the PCA9575
register is written to a known-good default state and SMA1/SMA2
properly report as active inputs with the expected frequency.

The behavior you describe (U.FL1/U.FL2 staying disconnected after
SMA direction change) is a pre-existing issue in
ice_dpll_sma_direction_set(), not in the initialization path.

I am addressing this in v2 of "[PATCH iwl-net] ice: fix U.FL pin
state set affecting paired SMA pin" with an expanded scope that
covers both directions of the SMA/U.FL pairing.

Is it OK like this?

Regards,
Petr