Re: [PATCH AUTOSEL 6.18] tools/power/turbostat: Fix microcode patch level output for AMD/Hygon

[Christian Ludloff]

> + if (get_msr(sched_getcpu(), MSR_IA32_UCODE_REV, &ucode_patch)) {

Intel prescribes a sequence of WRMSR(0x8B,0) + CPUID(1) + RDMSR.

This goes back to the original P6, where the upper half of the
BBL_CR_D3 L2 cache test register was abused to report the microcode
revision, and CPUID was abused to actually load the revision into said
MSR. Afaik the WRMSR(0x8B,0) is still required today.

turbostat has the prescribed CPUID(1) – by chance, a few lines earlier
– but it lacks the prescribed WRMSR(0x8B,0).

Also, note that the prescribed Intel sequence is neither required for
AMD, nor actually works for AMD – there the MSR is read-only.

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C.