Re: [PATCH v3 2/4] clk: renesas: r8a7740: Implement ZT/ZTR trace clock on R-Mobile A1

[Geert Uytterhoeven]

Hi Marek,

On Thu, 23 Apr 2026 at 01:38, Marek Vasut
<marek.vasut+renesas@xxxxxxxxxxx> wrote:
> Implement ZT trace bus and ZTR trace clock on the R-Mobile A1.
>
> Signed-off-by: Marek Vasut <marek.vasut+renesas@xxxxxxxxxxx>

Thanks for your patch!

> --- a/drivers/clk/renesas/clk-r8a7740.c
> +++ b/drivers/clk/renesas/clk-r8a7740.c
> @@ -37,6 +37,8 @@ static struct div4_clk div4_clks[] = {
>         { "zg", CPG_FRQCRA, 16 },
>         { "b", CPG_FRQCRA,  8 },
>         { "m1", CPG_FRQCRA,  4 },
> +       { "ztr", CPG_FRQCRB,  20 },

This is not 100% correct: ZTR has an optional /2 post-divider that is
controlled by the ZTRCKCR.CKSEL bit.   As the Coresight drivers do
not seem to care about the clock rate, I guess this is fine.

> +       { "zt", CPG_FRQCRB,  16 },
>         { "hp", CPG_FRQCRB,  4 },
>         { "hpp", CPG_FRQCRC, 20 },
>         { "usbp", CPG_FRQCRC, 16 },

Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
i.e. will queue in renesas-clk for v7.2.

Gr{oetje,eeting}s,

                        Geert


--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds