Re: [PATCH 3/3] PCI: altera: add Agilex 5 support

[Mahesh Vaidya]

On 24-04-2026 21:18, Bjorn Helgaas wrote:
> Adjust subject lines of both patches to match previous style
> (capitalize first word, e.g.,
>
>    PCI: altera: Add ...
Sure.

> On Fri, Apr 24, 2026 at 02:49:13AM -0700, Mahesh Vaidya wrote:
> > Add PCIe root port controller support for the Agilex 5 (V4) family
> > of SoC FPGAs.
>
> > +++ b/drivers/pci/controller/pcie-altera.c
> > @@ -12,6 +12,8 @@
> >   #include <linux/irqchip/chained_irq.h>
> >   #include <linux/irqdomain.h>
> >   #include <linux/init.h>
> > +#include <linux/bitfield.h>
> > +#include <linux/iopoll.h>
>
> Alphabetize these to match existing style.
Sure.

> > +static void aglx5_isr(struct irq_desc *desc)
> > +{
> > +	struct irq_chip *chip = irq_desc_get_chip(desc);
> > +	struct altera_pcie *pcie;
> > +	struct device *dev;
> > +	u32 status = 0;
> > +	int ret;
> > +
> > +	chained_irq_enter(chip, desc);
> > +	pcie = irq_desc_get_handler_data(desc);
> > +	dev = &pcie->pdev->dev;
> > +
> > +	ret = aglx5_indirect_readl(pcie, pcie->pcie_data->port_irq_status_offset, &status);
>
> Existing code fits in 80 columns, would be nice if this and a few more
> below did too.
I guess checkpatch should have warned it, I will recheck and fix them.