Re: [PATCH v4 05/13] iio: dac: ad5686: fix overlapping DMA buffers in I2C read

[Andy Shevchenko]

On Wed, Apr 29, 2026 at 02:07:35PM +0100, Rodrigo Alencar via B4 Relay wrote:
> 
> The TX and RX buffers in ad5686_i2c_read() both reference data[0], causing
> byte d8[1] to be shared between the TX buffer and the RX buffer. I2C
> controller drivers that map all message buffers for DMA before initiating
> the hardware transaction will map overlapping memory ranges with
> conflicting DMA directions (DMA_TO_DEVICE and DMA_FROM_DEVICE). This issue
> was reported by sashiko.

Not sure how this patch helps with that. The minimum granularity for DMA is
a cache line size. Do we have data[0] and data[1] be cache line separated?

It might be I miss something obvious, but this topic is always confusing
to me (DMA alignment).

-- 
With Best Regards,
Andy Shevchenko