RE: [PATCH v3 1/3] dt-bindings: PCI: imx6q-pcie: Add intr, aer and pme interrupts

[Hongxing Zhu]

> -----Original Message-----
> From: Krzysztof Kozlowski <krzk@xxxxxxxxxx>
> Sent: Thursday, April 30, 2026 4:04 PM
> To: Hongxing Zhu <hongxing.zhu@xxxxxxx>
> Cc: robh@xxxxxxxxxx; krzk+dt@xxxxxxxxxx; conor+dt@xxxxxxxxxx;
> bhelgaas@xxxxxxxxxx; Frank Li <frank.li@xxxxxxx>; l.stach@xxxxxxxxxxxxxx;
> lpieralisi@xxxxxxxxxx; kwilczynski@xxxxxxxxxx; mani@xxxxxxxxxx;
> s.hauer@xxxxxxxxxxxxxx; kernel@xxxxxxxxxxxxxx; festevam@xxxxxxxxx; linux-
> pci@xxxxxxxxxxxxxxx; linux-arm-kernel@xxxxxxxxxxxxxxxxxxx;
> devicetree@xxxxxxxxxxxxxxx; imx@xxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx
> Subject: Re: [PATCH v3 1/3] dt-bindings: PCI: imx6q-pcie: Add intr, aer and pme
> interrupts
> 
> On Thu, Apr 30, 2026 at 01:09:52PM +0800, Richard Zhu wrote:
> > Add 'intr', 'aer', and 'pme' interrupt entries to the i.MX6Q PCIe
> > binding to support PCIe event-based interrupts for general controller
> > events, Advanced Error Reporting, and Power Management Events respectively.
> >
> > These interrupts are optional for existing variants (imx6q, imx6sx,
> > imx6qp, imx7d, imx8mq, imx8mm, imx8mp) to maintain backward
> > compatibility with existing device trees.
> >
> > For fsl,imx95-pcie, all 5 interrupts (msi, dma, intr, aer, pme) are
> > mandatory due to hardware requirements.
> >
> > This introduces an ABI requirement for fsl,imx95-pcie. The i.MX95
> > hardware requires dedicated interrupt lines for AER, PME, and general
> > controller events due to its redesigned interrupt architecture. i.MX95
> > cannot function correctly without explicit interrupt routing for error
> > handling, power management and link event detection.
> 
> fsl,imx95-pcie was added more than two years ago, so how it cannot function
> correctly? Are you saying that for two years you had here completely broken
> code?
>
> If this wasn't tested for two years, how can we believe anything is tested now?
The basic PCIe functionality has been working since the initial fsl,imx95-pcie
support. However, AER (Advanced Error Reporting) and link up/down detection
were not previously enabled. This patch-set adds and verifies support for
these advanced features.

Best Regards
Richard Zhu
> 
> Best regards,
> Krzysztof