[tip: irq/drivers] dt-bindings: interrupt-controller: Repurpose binding for unreleased jh8100 for jhb100

[tip-bot2 for Changhuang Liang]

The following commit has been merged into the irq/drivers branch of tip:

Commit-ID:     a540d544db1c37d4c138b67384f235a85f79f060
Gitweb:        https://git.kernel.org/tip/a540d544db1c37d4c138b67384f235a85f79f060
Author:        Changhuang Liang <changhuang.liang@xxxxxxxxxxxxxxxx>
AuthorDate:    Wed, 15 Apr 2026 23:47:47 -07:00
Committer:     Thomas Gleixner <tglx@xxxxxxxxxx>
CommitterDate: Thu, 30 Apr 2026 12:53:04 +02:00

dt-bindings: interrupt-controller: Repurpose binding for unreleased jh8100 for jhb100

The StarFive JH8100 SoC was discontinued before production. The newly
taped-out JHB100 SoC uses the same interrupt controller IP.

Rename the binding file, compatible string, and MAINTAINERS entry from
"jh8100" to "jhb100". In JHB100 SoC, The clocks and resets are not operated
by users, but they exist in the hardware. Mark them as optional.

Signed-off-by: Changhuang Liang <changhuang.liang@xxxxxxxxxxxxxxxx>
Signed-off-by: Thomas Gleixner <tglx@xxxxxxxxxx>
Acked-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
Link: https://patch.msgid.link/20260416064751.632138-2-changhuang.liang@xxxxxxxxxxxxxxxx
---
 Documentation/devicetree/bindings/interrupt-controller/starfive,jh8100-intc.yaml | 61 -------------------------------------------------------------
 Documentation/devicetree/bindings/interrupt-controller/starfive,jhb100-intc.yaml | 49 +++++++++++++++++++++++++++++++++++++++++++++++++
 MAINTAINERS                                                                      |  2 +-
 3 files changed, 50 insertions(+), 62 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/starfive,jh8100-intc.yaml
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/starfive,jhb100-intc.yaml

diff --git a/Documentation/devicetree/bindings/interrupt-controller/starfive,jh8100-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/starfive,jh8100-intc.yaml
deleted file mode 100644
index ada5788..0000000
--- a/Documentation/devicetree/bindings/interrupt-controller/starfive,jh8100-intc.yaml
+++ /dev/null
@@ -1,61 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/interrupt-controller/starfive,jh8100-intc.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: StarFive External Interrupt Controller
-
-description:
-  StarFive SoC JH8100 contain a external interrupt controller. It can be used
-  to handle high-level input interrupt signals. It also send the output
-  interrupt signal to RISC-V PLIC.
-
-maintainers:
-  - Changhuang Liang <changhuang.liang@xxxxxxxxxxxxxxxx>
-
-properties:
-  compatible:
-    const: starfive,jh8100-intc
-
-  reg:
-    maxItems: 1
-
-  clocks:
-    description: APB clock for the interrupt controller
-    maxItems: 1
-
-  resets:
-    description: APB reset for the interrupt controller
-    maxItems: 1
-
-  interrupts:
-    maxItems: 1
-
-  interrupt-controller: true
-
-  "#interrupt-cells":
-    const: 1
-
-required:
-  - compatible
-  - reg
-  - clocks
-  - resets
-  - interrupts
-  - interrupt-controller
-  - "#interrupt-cells"
-
-additionalProperties: false
-
-examples:
-  - |
-    interrupt-controller@12260000 {
-      compatible = "starfive,jh8100-intc";
-      reg = <0x12260000 0x10000>;
-      clocks = <&syscrg_ne 76>;
-      resets = <&syscrg_ne 13>;
-      interrupts = <45>;
-      interrupt-controller;
-      #interrupt-cells = <1>;
-    };
diff --git a/Documentation/devicetree/bindings/interrupt-controller/starfive,jhb100-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/starfive,jhb100-intc.yaml
new file mode 100644
index 0000000..d8a0a38
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/starfive,jhb100-intc.yaml
@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/starfive,jhb100-intc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive External Interrupt Controller
+
+description:
+  StarFive SoC JHB100 contain a external interrupt controller. It can be used
+  to handle high-level input interrupt signals. It also send the output
+  interrupt signal to RISC-V PLIC.
+
+maintainers:
+  - Changhuang Liang <changhuang.liang@xxxxxxxxxxxxxxxx>
+
+properties:
+  compatible:
+    const: starfive,jhb100-intc
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  interrupt-controller: true
+
+  "#interrupt-cells":
+    const: 1
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - interrupt-controller
+  - "#interrupt-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    interrupt-controller@12260000 {
+      compatible = "starfive,jhb100-intc";
+      reg = <0x12260000 0x10000>;
+      interrupts = <45>;
+      interrupt-controller;
+      #interrupt-cells = <1>;
+    };
diff --git a/MAINTAINERS b/MAINTAINERS
index 2fb1c75..30626d0 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -25536,7 +25536,7 @@ F:	drivers/phy/starfive/phy-jh7110-usb.c
 STARFIVE JH8100 EXTERNAL INTERRUPT CONTROLLER DRIVER
 M:	Changhuang Liang <changhuang.liang@xxxxxxxxxxxxxxxx>
 S:	Supported
-F:	Documentation/devicetree/bindings/interrupt-controller/starfive,jh8100-intc.yaml
+F:	Documentation/devicetree/bindings/interrupt-controller/starfive,jhb100-intc.yaml
 F:	drivers/irqchip/irq-starfive-jh8100-intc.c
 
 STATIC BRANCH/CALL