[RESEND PATCH 13/16] PCI: qcom: Use FIELD_MODIFY()
From: Hans Zhang
Date: Thu Apr 30 2026 - 12:31:38 EST
Use FIELD_MODIFY() to remove open-coded bit manipulation.
No functional change intended.
Signed-off-by: Hans Zhang <18255117159@xxxxxxx>
---
drivers/pci/controller/dwc/pcie-qcom-common.c | 40 +++++++------------
drivers/pci/controller/dwc/pcie-qcom-ep.c | 6 +--
2 files changed, 16 insertions(+), 30 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-qcom-common.c b/drivers/pci/controller/dwc/pcie-qcom-common.c
index 5aa73c628737..0da73caf2011 100644
--- a/drivers/pci/controller/dwc/pcie-qcom-common.c
+++ b/drivers/pci/controller/dwc/pcie-qcom-common.c
@@ -30,20 +30,15 @@ void qcom_pcie_common_set_equalization(struct dw_pcie *pci)
reg = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF);
reg &= ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL;
- reg &= ~GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK;
- reg |= FIELD_PREP(GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK,
- speed - PCIE_SPEED_8_0GT);
+ FIELD_MODIFY(GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK, ®,
+ speed - PCIE_SPEED_8_0GT);
dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, reg);
reg = dw_pcie_readl_dbi(pci, GEN3_EQ_FB_MODE_DIR_CHANGE_OFF);
- reg &= ~(GEN3_EQ_FMDC_T_MIN_PHASE23 |
- GEN3_EQ_FMDC_N_EVALS |
- GEN3_EQ_FMDC_MAX_PRE_CURSOR_DELTA |
- GEN3_EQ_FMDC_MAX_POST_CURSOR_DELTA);
- reg |= FIELD_PREP(GEN3_EQ_FMDC_T_MIN_PHASE23, 0x1) |
- FIELD_PREP(GEN3_EQ_FMDC_N_EVALS, 0xd) |
- FIELD_PREP(GEN3_EQ_FMDC_MAX_PRE_CURSOR_DELTA, 0x5) |
- FIELD_PREP(GEN3_EQ_FMDC_MAX_POST_CURSOR_DELTA, 0x5);
+ FIELD_MODIFY(GEN3_EQ_FMDC_T_MIN_PHASE23, ®, 0x1);
+ FIELD_MODIFY(GEN3_EQ_FMDC_N_EVALS, ®, 0xd);
+ FIELD_MODIFY(GEN3_EQ_FMDC_MAX_PRE_CURSOR_DELTA, ®, 0x5);
+ FIELD_MODIFY(GEN3_EQ_FMDC_MAX_POST_CURSOR_DELTA, ®, 0x5);
dw_pcie_writel_dbi(pci, GEN3_EQ_FB_MODE_DIR_CHANGE_OFF, reg);
reg = dw_pcie_readl_dbi(pci, GEN3_EQ_CONTROL_OFF);
@@ -61,14 +56,10 @@ void qcom_pcie_common_set_16gt_lane_margining(struct dw_pcie *pci)
u32 reg;
reg = dw_pcie_readl_dbi(pci, GEN4_LANE_MARGINING_1_OFF);
- reg &= ~(MARGINING_MAX_VOLTAGE_OFFSET |
- MARGINING_NUM_VOLTAGE_STEPS |
- MARGINING_MAX_TIMING_OFFSET |
- MARGINING_NUM_TIMING_STEPS);
- reg |= FIELD_PREP(MARGINING_MAX_VOLTAGE_OFFSET, 0x24) |
- FIELD_PREP(MARGINING_NUM_VOLTAGE_STEPS, 0x78) |
- FIELD_PREP(MARGINING_MAX_TIMING_OFFSET, 0x32) |
- FIELD_PREP(MARGINING_NUM_TIMING_STEPS, 0x10);
+ FIELD_MODIFY(MARGINING_MAX_VOLTAGE_OFFSET, ®, 0x24);
+ FIELD_MODIFY(MARGINING_NUM_VOLTAGE_STEPS, ®, 0x78);
+ FIELD_MODIFY(MARGINING_MAX_TIMING_OFFSET, ®, 0x32);
+ FIELD_MODIFY(MARGINING_NUM_TIMING_STEPS, ®, 0x10);
dw_pcie_writel_dbi(pci, GEN4_LANE_MARGINING_1_OFF, reg);
reg = dw_pcie_readl_dbi(pci, GEN4_LANE_MARGINING_2_OFF);
@@ -76,13 +67,10 @@ void qcom_pcie_common_set_16gt_lane_margining(struct dw_pcie *pci)
MARGINING_SAMPLE_REPORTING_METHOD |
MARGINING_IND_LEFT_RIGHT_TIMING |
MARGINING_VOLTAGE_SUPPORTED;
- reg &= ~(MARGINING_IND_UP_DOWN_VOLTAGE |
- MARGINING_MAXLANES |
- MARGINING_SAMPLE_RATE_TIMING |
- MARGINING_SAMPLE_RATE_VOLTAGE);
- reg |= FIELD_PREP(MARGINING_MAXLANES, pci->num_lanes) |
- FIELD_PREP(MARGINING_SAMPLE_RATE_TIMING, 0x3f) |
- FIELD_PREP(MARGINING_SAMPLE_RATE_VOLTAGE, 0x3f);
+ reg &= ~MARGINING_IND_UP_DOWN_VOLTAGE;
+ FIELD_MODIFY(MARGINING_MAXLANES, ®, pci->num_lanes);
+ FIELD_MODIFY(MARGINING_SAMPLE_RATE_TIMING, ®, 0x3f);
+ FIELD_MODIFY(MARGINING_SAMPLE_RATE_VOLTAGE, ®, 0x3f);
dw_pcie_writel_dbi(pci, GEN4_LANE_MARGINING_2_OFF, reg);
}
EXPORT_SYMBOL_GPL(qcom_pcie_common_set_16gt_lane_margining);
diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c
index 257c2bcb5f76..56184e6ca6e6 100644
--- a/drivers/pci/controller/dwc/pcie-qcom-ep.c
+++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c
@@ -494,15 +494,13 @@ static int qcom_pcie_perst_deassert(struct dw_pcie *pci)
/* Set the L0s Exit Latency to 2us-4us = 0x6 */
offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
- val &= ~PCI_EXP_LNKCAP_L0SEL;
- val |= FIELD_PREP(PCI_EXP_LNKCAP_L0SEL, 0x6);
+ FIELD_MODIFY(PCI_EXP_LNKCAP_L0SEL, &val, 0x6);
dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, val);
/* Set the L1 Exit Latency to be 32us-64 us = 0x6 */
offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
- val &= ~PCI_EXP_LNKCAP_L1EL;
- val |= FIELD_PREP(PCI_EXP_LNKCAP_L1EL, 0x6);
+ FIELD_MODIFY(PCI_EXP_LNKCAP_L1EL, &val, 0x6);
dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, val);
dw_pcie_dbi_ro_wr_dis(pci);
--
2.34.1