Re: [PATCH v17 09/11] cxl: Update Endpoint AER uncorrectable handler

[Jonathan Cameron]

On Wed, 6 May 2026 10:43:02 -0700
Dave Jiang <dave.jiang@xxxxxxxxx> wrote:

> On 5/5/26 10:30 AM, Terry Bowman wrote:
> > The CXL cxl_core driver now implements protocol RAS support. PCI
> > uncorrectable (UCE) protocol errors, however, continue to be reported via
> > the AER capability and must still be handled by a PCI error recovery callback.
> > UCE handling is required to provide direction for recovery.
> > 
> > Replace the existing cxl_error_detected() callback in cxl/pci.c with a new
> > cxl_pci_error_detected() implementation that handles uncorrectable AER PCI
> > protocol errors.
> > 
> > The handler decides solely based on the pci_channel_state_t parameter and
> > does not access PCIe AER capability registers from .error_detected, matching
> > the pattern used by other drivers including the NVMe and ixgbe drivers.
> > CXL.cachemem-corrupting protocol errors are routed separately through the
> > AER-CXL kfifo to cxl_handle_proto_error(), so cxl_pci does not need to
> > second-guess the AER core's classification.
> > 
> > claude-opus-4.7 was used for research on PCI error state transitions and
> > requirements.
> > 
> > Assisted-by: Claude:claude-opus-4.7
> > Signed-off-by: Terry Bowman <terry.bowman@xxxxxxx>
...

> > ---
> >  drivers/cxl/core/ras.c | 43 ++++++++++++++++--------------------------
> >  drivers/cxl/cxlpci.h   |  8 ++++----
> >  drivers/cxl/pci.c      |  6 +++---
> >  3 files changed, 23 insertions(+), 34 deletions(-)
> > 
> > diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c
> > index 5cc4087c2807..a98ce0f412ad 100644
> > --- a/drivers/cxl/core/ras.c
> > +++ b/drivers/cxl/core/ras.c
> > @@ -253,38 +253,27 @@ bool cxl_handle_ras(struct device *dev, u64 serial, void __iomem *ras_base)
> >  	return true;
> >  }
> >  
> > -pci_ers_result_t cxl_error_detected(struct pci_dev *pdev,
> > -				    pci_channel_state_t state)
> > +pci_ers_result_t cxl_pci_error_detected(struct pci_dev *pdev,
> > +					pci_channel_state_t state)
> >  {
> > -	struct cxl_dev_state *cxlds = pci_get_drvdata(pdev);
> > -	struct cxl_memdev *cxlmd = cxlds->cxlmd;
> > -	struct device *dev = &cxlmd->dev;
> > -	bool ue;
> > +	struct cxl_dport *dport;
> > +	struct cxl_port *port __free(put_cxl_port) =
> > +		find_cxl_port_by_dev(&pdev->dev, &dport);  
> 
> Move this to right before 'port' is being checked. It's ok to do inline var declaration with __free().

With that done LGTM
Reviewed-by: Jonathan Cameron <jic23@xxxxxxxxxx>