[PATCH v2 0/4] riscv: spacemit: k3: some clock fixes related to PCIe

[Yixun Lan]

Here are some fixes for previous patch set in order to make PCIe work,
Add PCIe DBI clock which was missing, Fix the parent clock, And correct
the PCIe Clock CTRL register offset.

Signed-off-by: Yixun Lan <dlan@xxxxxxxxxx>
---
Changes in v2:
- Drop Fixes tag in patch 1, 2, which is not necessary
- Re-arrange the order of patches, move 1, 2 as last two which is not
  strictly bug fix
- Link to v1: https://lore.kernel.org/r/20260430-06-pci-clk-fix-v1-0-32fdc77c02ab@xxxxxxxxxx

---
Yixun Lan (4):
      clk: spacemit: k3: Switch to pll2_d6 as parent for PCIe clock
      clk: spacemit: k3: Fix PCIe clock register offset
      dt-bindings: soc: spacemit: k3: Add PCIe DBI clock IDs
      clk: spacemit: k3: Add PCIe DBI clock

 drivers/clk/spacemit/ccu-k3.c                  | 30 +++++++++++++++++---------
 include/dt-bindings/clock/spacemit,k3-clocks.h |  5 +++++
 include/soc/spacemit/k3-syscon.h               |  4 ++--
 3 files changed, 27 insertions(+), 12 deletions(-)
---
base-commit: 254f49634ee16a731174d2ae34bc50bd5f45e731
change-id: 20260430-06-pci-clk-fix-e60487b07607

Best regards,
--  
Yixun Lan <dlan@xxxxxxxxxx>