Re: [PATCH v1 2/5] clk: tegra20: reparent dsi clock to pll_d_out0

[Svyatoslav Ryhel]

пн, 11 трав. 2026 р. о 10:48 Svyatoslav Ryhel <clamor95@xxxxxxxxx> пише:
>
> Reparent DSI clock to PLLD_OUT0 instead of directly descend from PLLD.
>
> Signed-off-by: Svyatoslav Ryhel <clamor95@xxxxxxxxx>
> ---
>  drivers/clk/tegra/clk-tegra20.c | 5 ++---
>  1 file changed, 2 insertions(+), 3 deletions(-)
>

Please ignore this. This patch was send by mistake. Sorry for inconvenience.