[tip: irq/urgent] irqchip/meson-gpio: Use the correct register in meson_s4_gpio_irq_set_type()

[tip-bot2 for Xianwei Zhao]

The following commit has been merged into the irq/urgent branch of tip:

Commit-ID:     5363b67ac8ebcc3e227dbf59fc8061949109841d
Gitweb:        https://git.kernel.org/tip/5363b67ac8ebcc3e227dbf59fc8061949109841d
Author:        Xianwei Zhao <xianwei.zhao@xxxxxxxxxxx>
AuthorDate:    Fri, 08 May 2026 07:36:54 
Committer:     Thomas Gleixner <tglx@xxxxxxxxxx>
CommitterDate: Mon, 11 May 2026 15:22:48 +02:00

irqchip/meson-gpio: Use the correct register in meson_s4_gpio_irq_set_type()

meson_s4_gpio_irq_set_type() uses the both-edge trigger register for
configuring level type and single edge mode interrupts, which is not
correct.

Use REG_EDGE_POL instead.

Fixes: bbd6fcc76b39 ("irqchip: Add support for Amlogic A4 and A5 SoCs")
Signed-off-by: Xianwei Zhao <xianwei.zhao@xxxxxxxxxxx>
Signed-off-by: Thomas Gleixner <tglx@xxxxxxxxxx>
Cc: stable@xxxxxxxxxxxxxxx
Link: https://patch.msgid.link/20260508-a9-gpio-irqchip-v1-1-9dc5f3e022e0@xxxxxxxxxxx
---
 drivers/irqchip/irq-meson-gpio.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-gpio.c
index f722e9c..74a376e 100644
--- a/drivers/irqchip/irq-meson-gpio.c
+++ b/drivers/irqchip/irq-meson-gpio.c
@@ -415,8 +415,7 @@ static int meson_s4_gpio_irq_set_type(struct meson_gpio_irq_controller *ctl,
 	if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
 		val |= BIT(ctl->params->edge_single_offset + idx);
 
-	meson_gpio_irq_update_bits(ctl, params->edge_pol_reg,
-				   BIT(idx) | BIT(12 + idx), val);
+	meson_gpio_irq_update_bits(ctl, REG_EDGE_POL, BIT(idx) | BIT(12 + idx), val);
 	return 0;
 };