[PATCH 1/2] arm64: dts: qcom: ipq9650: add the SMMU device

[Kathiravan Thirumoorthy]

Add and enable the support for the SMMU500 found in the IPQ9650 SoC.

Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@xxxxxxxxxxxxxxxx>
---
 arch/arm64/boot/dts/qcom/ipq9650.dtsi | 42 +++++++++++++++++++++++++++++++++++
 1 file changed, 42 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/ipq9650.dtsi b/arch/arm64/boot/dts/qcom/ipq9650.dtsi
index 88bc77009ca0..3e7527609591 100644
--- a/arch/arm64/boot/dts/qcom/ipq9650.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq9650.dtsi
@@ -364,6 +364,48 @@ frame@f42d000 {
 				status = "disabled";
 			};
 		};
+
+		iommu@15000000 {
+			compatible = "qcom,ipq9650-smmu-500", "qcom,smmu-500", "arm,mmu-500";
+			reg = <0x0 0x15000000 0x0 0x40000>;
+
+			interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 646 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 647 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 648 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 649 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 650 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 651 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 653 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 655 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 659 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 660 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 663 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 667 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 668 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 670 IRQ_TYPE_LEVEL_HIGH 0>;
+
+			#iommu-cells = <2>;
+			#global-interrupts = <1>;
+		};
 	};
 
 	timer {

-- 
2.34.1