[PATCH v2 04/12] dt-bindings: clock: Add peripheral-0 domain PLL clock

[Changhuang Liang]

Add peripheral-0 domain PLL clock for StarFive JHB100 SoC.

Signed-off-by: Changhuang Liang <changhuang.liang@xxxxxxxxxxxxxxxx>
---
 include/dt-bindings/clock/starfive,jhb100-crg.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/include/dt-bindings/clock/starfive,jhb100-crg.h b/include/dt-bindings/clock/starfive,jhb100-crg.h
index 98b3cf28b677..37a4535472bf 100644
--- a/include/dt-bindings/clock/starfive,jhb100-crg.h
+++ b/include/dt-bindings/clock/starfive,jhb100-crg.h
@@ -14,6 +14,9 @@
 #define JHB100_SYS0PLL_PLL4_OUT				2
 #define JHB100_SYS0PLL_PLL5_OUT				3
 
+/* PER0PLL clocks */
+#define JHB100_PER0PLL_PLL6_OUT				0
+
 /* SYS0CRG clocks */
 #define JHB100_SYS0CLK_BMCPCIERP_NCNOC_MAIN		17
 #define JHB100_SYS0CLK_BMCPCIERP_NCNOC_CFG		18
-- 
2.25.1